Synchronous DRAM modules including multiple clock out signals fo

Details Synchronous DRAM modules including multiple clock out signals fo Synchronous DRAM modules including multiple clock out signals fo

1996-08-15

1999-11-23

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711115, 711154, 711167, 36523003, G06F 1200, G06F 1300

Patent

active

059918500

ABSTRACT:
Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.

REFERENCES:
patent: 5089993 (1992-02-01), Neal et al.
patent: 5228132 (1993-07-01), Neal et al.
patent: 5261068 (1993-11-01), Gaskins et al.
patent: 5287327 (1994-02-01), Takasugi
patent: 5440552 (1995-08-01), Hirano
patent: 5513135 (1996-04-01), Dell et al.
patent: 5524232 (1996-06-01), Hajeer
patent: 5586129 (1996-12-01), Chan
patent: 5634803 (1997-06-01), Cheng et al.
patent: 5686730 (1997-11-01), Laudon et al.
patent: 5696031 (1997-12-01), Wark

Affiliated with

Also associated with

Rating

Synchronous DRAM modules including multiple clock out signals fo does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronous DRAM modules including multiple clock out signals fo, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronous DRAM modules including multiple clock out signals fo will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1235178