Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-03-03
2001-07-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S240000, C365S236000
Reexamination Certificate
active
06262938
ABSTRACT:
This application relies for priority upon Korean Patent Application Nos. 99-6939 and 99-20821, filed on Mar. 3, 1999, and Jun. 5, 1999, respectively, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous DRAM (SDRAM). More particularly, the present invention relates to an SDRAM having a column access strobe (CAS) latency, as well as a method for controlling the CAS latency.
In general, an SDRAM is synchronized with a clock signal input from outside the circuit and so the read or write operation of the SRAM is controlled.
FIG. 13
describes the latency from the application of a row access command or a column access command to the output of data.
The number of clock cycles of an external clock signal from the application of a row access command to the output of first data is called the RAS latency (RL). The number of clock cycles of the external clock signal from the application of a column access command to the output of the first data is called the CAS latency (CL). The number of clock cycles of the external clock signal from the application of the row access command to the application of the column access command with respect to the same memory bank is called the RAS-CAS latency (RCL). The relationship between RCL, RL, and CL is shown in Equation 1.
RL=RCL+CL
(1)
When the minimum value of the RAS latency in the frequency of a specific external clock signal is RL
min
, then RL must satisfy Equation 2.
RL≧RL
min
(2)
When the minimum value of the CAS latency in the frequency of the specific external clock signal is CL
min
, then RCL
min
(the minimum RAS-CAS latency) is expressed as shown in Equation 3.
RCL
min
=RL
min
−CL
min
(3)
In a system using an SDRAM, a function of normally outputting data even when RCL<RCL
min
, namely, in posted CAS latency, is required in order to improve the performance of the system. In this application, posted CAS latency refers to the fact that the CAS command comes earlier than the conventional RCL
min
. In other words,RL≧RL
min
, which is generally the product specification, must be satisfied even when RCL<RCL
min
. In order to satisfy the equality RL≧RL
min
in the posted CAS latency, the CAS latency CL must satisfy Equation 4
CL>CL
min
+(
RCL
min
−RCL
) (4)
In a conventional SDRAM, since the specification of (RCL
min
−RCL)<0 is required, it is enough to determine the CL, which guarantees the minimum CAS latency CL
min
by a mode register set (MRS) command. However, in a posted CAS state, it is possible to input a CAS command (including a column address command), which controls an appropriate delay time and the latency of a data path only when each of the values in Equation 4, i.e., (RCL
min
−RCL) and CL
min
, are known.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronous DRAM (SDRAM) by which it is possible to perform a posted column access strobe (CAS) command.
It is another object of the present invention to provide a method for outputting data using the SDRAM.
Accordingly, to achieve the first object, A synchronous DRAM (SDRAM), operating in synchronization with a clock signal, is provided. The SDRAM comprises a memory bank having a plurality of memory cells arranged in rows and columns, a column decoder for selecting a column of the memory bank, a column address input port for inputting a column address that selects the column of the memory bank, a first shift register for delaying the column address by a first number of delay clock cycles between the column address input port and the column decoder, and a delay counter for sensing the number of clock cycles RCL of the clock signal from the application of the row access command to the application of the column access command with respect to the same bank, and for providing a first delay clock control signal to the first shift register. RL
min
is the minimum number of clock cycles of the clock signal required from the application of a row access command to the output of the data of the memory, and CL
min
is the minimum number of clock cycles of the clock signal required from the application of a column access command to the output of the data of the memory cell. The first delay clock control signal has information on the difference between RCL and (RL
min
−CL
min
), and the first number of delay clock cycles is determined in response to the difference between RCL and (RL
min
−CL
min
).
The first shift register my comprise a plurality of registers serially coupled to each other for continuously transmitting the column address in response to the clock signal of every period, and a multiplexer for selectively providing one signal among the output signals of the plurality of registers to the column decoder. The registers are preferably D flip-flops.
The delay counter may comprise a down counter for reducing the value of (RL
min
−CL
min
) by 1 in response to the clock signal, a register for providing a first delay clock control signal having information on an output value stored as an output value of the down counter when the column access command is generated or an output value of the down counter having the value of 0 to the first shift register after the row access command is generated, a clock controller that is disabled when the output value of the down counter is 0, for providing a first clock control signal which is enabled by the generation of the row access command and responds to the clock signal to the down counter, and a logic unit disabled by the generation of the column access command, for providing a second clock control signal that is enabled by the generation of the row access command and responds to the first clock control signal. The delay counter may further comprise an RCL measuring unit for providing an output signal activated by the generation of the row access command and disabled by the generation of the column access command to the logic unit.
The synchronous DRAM may further comprise a second shift register for delaying the output data of a selected memory cell by CL
min
, and a buffer for buffering the output signal of the second shift register and delaying the output signal of the second shift register by a second number of delay clock cycles in response to a second predetermined delay clock control signal.
The SDRAM may further comprising a buffer controller for generating a second delay clock control signal for controlling the buffer. The buffer controller itself may comprise a first register for delaying the column access command by the second number of delay clock cycles and outputting the delayed column access command, every cycle of the clock signal, and a second register for delaying the output signal of the first register by CL
min
and generating a second delay control signal for controlling the buffer.
A synchronous DRAM (SDRAM) operating in synchronization with a clock signal, is also provided. The SDRAM comprises a memory bank having a plurality of memory cells arranged in rows and columns, a column decoder for selecting a column of the memory bank, a pair of bit lines for outputting data from the selected column, a sense amplifier for amplifying the data of the bit lines, a column address input port for inputting a column address for selecting the column of the memory bank, a first shift register for delaying the column address by a first number of delay clock cycles between the column address input port and the column decoder, and a delay counter for providing a first delay clock control signal having information on the difference between RCL and SAE to the first shift register. RCL is the number of clock cycles of the clock signal from the application of a row access command to the application of a column access command with respect to the same bank; SAE is the number of clock cycles of the clock signal from the application of the row access command to the point of time at which the
Lee Dong-yang
Lee Jung-bae
Shin Choong-Sun
Jones Volentine, L.L.C.
Le Thong
Nelms David
Samsung Electronics Co,. Ltd.
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