Synchronous DRAM controller with memory access commands timed fo

Details Synchronous DRAM controller with memory access commands timed fo Synchronous DRAM controller with memory access commands timed fo

1995-10-20

1997-11-04

Swann, Tod R.

395432, 395433, G06F 1314

Patent

active

056849788

ABSTRACT:
For an synchronous dynamic access memory ("S-DRAM") system including a memory assembly with multiple memory units, data access commands are placed on a command bus at specific times to facilitate gapless data bus operation. After receipt of a first memory access request, a first memory access command is issued on the command bus to exchange a first data string having a first length with a first one of the memory units. Subsequently, receipt occurs of a second memory access request is to exchange a second data string, of a second length, with a second one of the memory units. A determination is made of an earliest possible time for placement of a second memory access command upon the command bus; this considers various factors, such as the first length, data bus availability, command bus availability, and any predetermined delay in placement of the first data string onto the data bus. Accordingly, the second memory access command is placed upon the command bus at the determined time. After the first data string leaves the data bus, any exchange of data between the first memory unit and the data bus may be prevented for a predetermined time.

REFERENCES:
patent: 4323965 (1982-04-01), Johnson et al.
patent: 4376972 (1983-03-01), Johnson et al.
patent: 5263003 (1993-11-01), Cowles et al.
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5539696 (1996-06-01), Patel
patent: 5560000 (1996-09-01), Vogley
patent: 5598374 (1997-01-01), Rao
patent: 5600605 (1997-02-01), Schaefer
Jones, Fred et al. "A New Era of Fast Dynamic RAMs", IEEE Spectrum, pp. 43-49, Oct. 1992.
Takai, Yasuhiro et al. "250 Mbyte/s Synchronous DRAM Using a 3-Stage-Pipelined Architecture", IEEE Journal of Solid-State Circuits, pp. 426-431, Apr. 1994.
Sunaga, Toshio et al. "A Full Bit Prefetch Architecture for Synchronous DRAM's", IEEE Journal of Solid-State Circuits, pp. 998-1005, Sep. 1995.

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