Synchronous digital transmission system having justification cir

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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375363, 370506, H04J 307, H04L 700

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active

057815976

ABSTRACT:
A synchronous digital transmission system has network nodes each operating at a respective fixed internal clock rate, each with a justification device for adapting an incoming signal to the respective fixed internal clock rate thereof by positive or negative justification actions, and for controlling a memory device which stores payload bytes of a frame of the incoming signal and outputs the payload bytes at the internal clock rate of a respective network node. The justification device has a first circuit (10) for counting incoming/outgoing frame bytes and calculating at sampling instants (T.sub.i) a difference value (.DELTA..sub.i) and a change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i), has a second circuit (20) for calculating a control value (OFFSET) which is dependent on the change (.DELTA..sub.i -.DELTA..sub.i-1) in the difference value (.DELTA..sub.i) and on a correction factor (LEAK), and has a third circuit (30) for comparing at the sampling instants (T.sub.i) the control value (OFFSET) with an upper threshold (U.sub.-- THRESH) and a lower threshold (L.sub.-- THRESH), and for initiating either a positive or negative justification action respectively if the control value (OFFSET) is either less than the lower threshold (L.sub.-- THRESH) or greater than the upper threshold (U.sub.-- THRESH).

REFERENCES:
patent: 5172376 (1992-12-01), Chopping et al.
patent: 5343476 (1994-08-01), Urbansky
patent: 5457717 (1995-10-01), Bellamy
"Jitter Reduction for Asynchronous Network Application of Synchronous Digital Hierachy" by Yoshinori Rokugo, Electronics & Communications in Japan, Part 1, vol. 76, No. 5, 1993.
"Methodology and Results of Synchronous Digital Hierarchy Network Payload Jitter Simulation" by Peter Sholander, Henry L. Owen, Simulation, Jan. 1995, pp. 34-41.
"Synchronous digital hierarchy network pointer simulation" by Henry Owen, Thomas M. Klett, Computer Networks and ISDN Systems 26 (1994) 481-491.

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