Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-11-19
2003-08-05
Bayard, Emmanuel (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
Reexamination Certificate
active
06603831
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to modems and more particularly to data transmitters used in such modems.
As is known in the art, modems are used to transmit data between a pair of stations. One method for such data transfer is with an Asynchronous Digital Subscriber Loop ADSL. With ADSL, a central office transmits data to a remote terminal in a downstream signal and the remote terminal transmits data to the central office in an upstream signal; the bandwidth of the upstream signal being greater than the bandwidth of the downstream signal. In each stream, however, the data from a data source is transmitted at a frame rate determined by the quality of the transmission line. Since, however, the input data rate may differ from the ADSL data frame rate, byte stuffing and robbing is performed in order to equalize the data source rate and the modem line rate; that is, byte robbing and stuffing is used to insure that each frame had the same number of data bytes per frame.
An alternative technique used to perform this rate adaptation function is to.,send asynchronous ATM (Asynchronous Transfer Mode) traffic across an ATM Utopia interface. In such an arrangement, the combination of asynchronous handshaking and idle cell generation and deletion perform the rate matching function instead of byte stuffing and robbing. The ability to perform rate adaptation using byte stuffing and robbing is no longer necessary when sending ATM traffic. This technique, however, does not lend itself to interface with traditional Bit Error Rate tester equipment and requires the ATM transmission convergence layer to be integrated into the physical layer.
More particularly, referring to
FIG. 1
, the transmitter
10
of a modem at one station and receiver
12
of a modem at a second station of an ADSL system is shown. Here, the transmitter
10
includes a data source
14
, a buffer
16
, here a First-In/First Out (FIFO), and a framer
18
, arranged as shown. The data from the data source
14
is clocked into the FIFO
16
in response to the clock pulses fed thereto from the data source
14
. The clock pulse rate varies from 0 to about 10 MBtyes per second (MBps). The framer
18
produces framed data at the ADSL line rate, which as noted above, is a function of the quality of the line connecting the transmitter
10
and the receiver
12
. More particularly, a burst of data is “pulled”, or retrieved from, the FIFO
16
in response to a strobe signal supplied by the framer
18
. Since the data input rate to the FIFO
16
from data source
14
is asynchronous with respect to the frame rate, byte stuffing or robbing is performed by the framer
18
in order to equalize the rates. This function is performed by a “stuff and rob” section using a level signal from the FIFO
16
to determine if the input rate is lower or higher than the outgoing ADSL line, or frame rate. If the level increases, then the input rate exceeds the ADSL internal rate and an additional byte is passed to the next ADSL frame in a predetermined byte position and signalled in a fast byte or sync byte. That is the signalling that a byte has been stuffed or robbed is passed in the fast byte for the fast data and the synch byte for interleaved data.
In the receiver
12
, the received data passing through a de-framer
20
which performs a de-stuffing and de-robbing process. Synch control information, from either the fast or the synch byte, depending on whether the data comes from the fast or interleaved path, is used to determine if the last byte should be blocked from or if additional bytes should be added to the FIFO. Based upon the Synch control information, the output of the de-framer
20
is gated into a FIFO
22
. The data is clocked out of the FIFO
20
using a smooth clock generated by a clock pulse generator
24
which can be implemented using a digital phase-locked-loop (DPLL). The clock rate of the clock pulse generator
24
is controlled by the level of the FIFO
22
in order to prevent overflowing of the FIFO
22
.
Thus, with the system shown in
FIG. 1
, the transmit path has stuff or rob bytes in the ADSL framing structure to match the ADSL data line rate thereby reducing the data transfer efficiency of the system.
SUMMARY OF THE INVENTION
In accordance with the present invention, a system is provided having a source of data. The data is transmitted in response to clock pulses. A buffer is provided having a data storage capacity for storing the data transmitted by the source of data. The data is stored in response to the clock pulses. A framer is provided for retrieving the stored data in response to a strobe signal produced by the framer and fed to the buffer. The buffer produces a control signal representative of the fill/empty state of the buffer. A clock pulse generator is provided for producing the clock pulses for the data source and the buffer at a rate selected in accordance with the control signal. The data stored in the buffer is read from the buffer in response to the strobe signal and such data read from the buffer is supplied to the framer in response to the strobe signal.
With such an arrangement, the data provided by the data source and the data written to the buffer are controlled by a common clock signal, which has a rate which is a function of the level of the buffer, thereby ensuring rate matching between the data source rate and the rate data is read from the buffer. Thus, byte stuffing and robbing is no longer required thereby increasing the efficiency of the data transfer.
In accordance with one embodiment of the invention, the clock pulse generator includes a digital phase lock loop which locks the frequency of the input data to the rate at which the framer draws data from the FIFO.
In accordance with one embodiment of the invention, a data transmitter is provided. The transmitter includes a source of data. The data is transmitted in response to clock pulses. A buffer having a data storage capacity is provided for storing the data transmitted by the source of data, such data being stored in response to the clock pulses. A framer is provided for retrieving the stored data in response to a data strobe signal produced by the framer and fed to the buffer. The buffer produces a control signal representative of the fill/empty state of the buffer. A fill/empty level signal and superframe strobe signal are fed to the clock pulse generator. The superframe strobe signal samples the fill/empty state of the buffer and produces a control signal representative of the sampled level (i.e., fill/empty state) of the buffer. A clock pulse generator is provided for producing the clock pulses for the data source and the buffer at a rate selected in accordance with the control signal. The data stored in the buffer is read from the buffer in response to the data strobe signal from the framer and such read data from the buffer is supplied to the framer in response to the strobe signal.
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patent: 5204882 (1993-04-01), Chao et al.
patent: 5473665 (1995-12-01), Hall et al.
patent: 5778218 (1998-07-01), Gulick
patent: 5802122 (1998-09-01), Niegel
patent: 6055248 (2000-04-01), Kobayashi
patent: 6128761 (2000-10-01), Benayoun et al.
patent: 6219730 (2001-04-01), Nguyen
patent: 6353635 (2002-03-01), Montague et al.
patent: 6363073 (2002-03-01), Nichols
Analog Devices Inc.
Bayard Emmanuel
Samuels , Gauthier & Stevens, LLP
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