Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1997-05-21
2002-03-26
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000, C711S154000, C365S233100, C365S194000, C365S189040
Reexamination Certificate
active
06363465
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a synchronous semiconductor memory device utilizing the latency technique, and more specifically to a data transfer system and data transfer method for transferring data through multiple data transfer stages under pipeline control.
Recently, there has been put into practical use semiconductor memory devices, such as synchronous dynamic random access memories (“SDRAMs”), in which data transfer control is simplified and high-speed data transfer is attained by synchronizing the control process with a clock signal. In the conventional SDRAM, a latency technique is used to enhance the clock frequency by masking (or apparently disregarding) the time required to output data from the memory cell to the exterior of the device. The latency indicates the minimum number of cycles required from the cycle in which an address is fetched to the cycle in which the data specified by the address is output. Such conventional SDRAMs are disclosed in Japanese Patent Application KOKAI Publication No. 5-2873 (corresponding to U.S. Pat. No. 5,313,437) and Japanese Patent Application KOKAI Publication No. 6-76563 (corresponding to U.S. Pat. No. 5,392,254).
FIG. 27
shows the relation between an external clock signal CLK and data output Dout in one case where the latency is “4” (LTC=4) and another case where the latency is “1” (LTC=1). If access is started at the rise of the clock at t0, the data transfer time T required for outputting the first data item of a series of data items is the same regardless of the latency because the data transfer time is determined by the characteristics of the memory device itself. If the latency is increased and the memory is controlled by a clock of constant period, more cycles are allotted to the data transfer time so that the clock period can be shortened and a high-frequency clock can be used to output the data. With a high-frequency clock, memory access and data transfer can be performed at a high speed in synchronism with the high-frequency clock, and the amount of data output per time unit can be increased, as can be understood from FIG.
27
.
When the latency is “1”, the data transfer operation from the rise of the external clock signal CLK to the output of data can be performed as a sequence of operations. On the other hand, when the latency is “4”, a plurality of data items are present in the same data transfer path, so a method for simultaneously transferring the data items in one block or a pipeline method for transferring the data must be used. In the pipeline method, the data transfer path is divided into segments, the data items in the segments are simultaneously transferred to construct a pipeline stage, and then the data is shifted between segments in a time sharing fashion. Because it is not necessary to previously determine the data block in the pipeline method, the data to be transferred can be freely selected for each clock cycle. However, if the latency is changed when the pipeline method is being used to transfer the data, the following problem occurs.
When a memory device using the pipeline method an and having a latency of “4” is changed from a high-frequency clock to a low-frequency clock, the apparent data transfer time is made longer if the latency is not changed. But, if the latency is changed from “4” to “1”, the number of stages in the data transfer pipeline must be changed so as to complete the data transfer in the cycle of the latency. Thus, the number of stages in the pipeline must be changed for each change in the latency. However, in order to change the number of pipeline stages, drastic changes must be made in the circuit construction and operation timing of the memory device. Thus, for each latency to be selectively used, pipeline control and operation timing for that latency must be designed into the device, so the data transfer system and the semiconductor memory device become complicated. Furthermore, the system must be re-designed to allow a latency other than the latencies already designed into the device to be used, so it is extremely difficult to flexibly cope with various latency requirements.
As explained above, in the conventional synchronous memory device using the pipeline-type data transfer system, the number of pipeline stages must be changed each time the latency is changed, and this requires drastic changes in the circuit construction and operation timing of the device. Further, in the conventional synchronous memory device using the latency technique, in order to use a latency other than the latencies already designed into the device, the memory device must be re-designed so it is extremely difficult to provide a device that can flexibly satisfy various latency requirements.
BRIEF SUMMARY OF THE INVENTION
In view of these problems, it is an object of the present invention to remove the above-mentioned drawbacks and to provide a pipeline-type data transfer system and data transfer method in which the latency can be changed without changing the number of data transfer stages or the control of the individual data transfer stages, so that various latency requirements can be easily satisfied.
Another object of the present invention is to provide a synchronous semiconductor memory device that can easily cope with a latency other than the latencies previously taken into consideration so that various latency requirements can be flexibly satisfied, and a memory system using the synchronous semiconductor memory device.
To achieve this object, a first preferred embodiment of the present invention provides a data transfer system that includes a system having successive stages connected in series. Each of the stages performs a partial operation necessary for transferring data in synchronism with a control clock, and the system transfers data by sequentially operating the stages and performs pipeline control to allow two or more stages to simultaneously transfer data. Also included is a clock generating circuit for generating internal clock signals based on an external clock signal supplied to the system, and a clock switching circuit for selectively switching the external clock signal and the internal clock signals generated by the clock generating circuit to control the operation of each of the stages.
In one embodiment, the clock generating circuit generates the internal clock signals based on a latency of the system, with the latency indicating the number of external clock cycles from the start of data access to data output. Further, the clock generating circuit generates the internal clock signals by sequentially delaying the external clock signal.
In another embodiment, there is a first mode in which all of the stages are controlled by the external clock signal, and a second mode in which only a first stage of the successive stages is controlled by the external clock signal and the other stages are controlled by the internal clock signals generated by the clock generating circuit.
In yet another embodiment, there is a mode in which a first stage and at least one intermediate stage of the successive stages are controlled by the external clock signal, and the other stages are controlled by the internal clock signals generated by the clock generating circuit.
Because the clock generating circuit generates the internal clock signals based on the external clock signal and the clock switching circuit selectively switches the external clock signal and the internal clock signals to change the clock signals that control the stages so as to change the latency, it becomes possible to easily cope with a change in the latency without having to change the number of data transfer segments or the control of the individual data transfer stages. Additionally, if the internal clock signals are generated based on the latency of the system, it becomes possible to easily generate the internal clock signals corresponding to that latency. And if the internal clock signals are generated by sequentially delaying the external clock signal, it becomes possible to more easily ge
Bataille Pierre-Michel
Hogan & Harston, L.L.P.
Kabushiki Kaisha Toshiba
Kim Matthew
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