Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-09-22
2001-07-10
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S111000, C711S163000, C711S167000, C713S400000, C365S233100
Reexamination Certificate
active
06260106
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to data storage systems, and more particularly to synchronous data storage systems that access data by application of command and address information packets.
BACKGROUND OF THE INVENTION
The increasing computing power of electronic systems has given rise the need for data storage systems (such as a system random access memory (RAM)) of increased data bandwidth. One way to address this need is to utilize data storage systems that employ synchronous memory devices. Synchronous memory devices, such as synchronous dynamic RAMs (SDRAMs) can provide pipeline data accesses that can include bursts of data, thereby increasing the overall rate at which data can be read from, or written into a data storage system, thereby increasing the overall data bandwidth of the system.
While the use of synchronous memory devices can improve data access rates, there still remains a need for systems that can provide even greater data bandwidths. At the cost of utilizing a more complex controller, one way to further improve the data bandwidth of a system, is to employ a packet-based data storage system. Packet-based data storage systems utilize command and address “packets” of information that are transmitted by a controller to one or more packet-based data storage devices. With the appropriate use of command and address packets, the amount of time a data bus is idle can be minimized, and can thereby increase data bandwidth even more.
An example of a prior art packet-based data storage system is set forth in FIG.
1
and designated by the general reference character
100
. The data storage system
100
is shown to include a controller
102
coupled to a number of data storage modules
104
-
0
to
104
-n. The controller
102
issues command and address data packets to the storage modules (
104
-
0
to
104
-n) by way of a command link
106
. Data are written to, and read from the storage modules (
104
-
0
to
104
-n) by way of a data link
108
. In the particular arrangement of
FIG. 1
, the command link
106
is a one-way link, while the data link is a two-way link.
To synchronize timing between the controller
102
and its associated storage modules (
104
-
0
to
104
-n), the command link
106
can include a command clock which will indicate to the storage modules (
104
-
0
to
104
-n) when to latch command and address information. Similarly, the data link
108
can include a data clock which indicates when read data can be latched by the controller
102
, and when write data can be latched by a given storage module (
104
-
0
to
104
-n).
The storage modules (
104
-
0
to
104
-n) can each include a specialized memory device, such as a dynamic RAM (DRAM) that includes the necessary circuits for interpreting command and address packets and issuing data and data clock signals. Alternatively, the storage modules (
104
-
0
to
104
-n) can have a “deeper” arrangement, and include multiple memory devices arranged in parallel and/or in series.
An example of a deeper storage module is set forth in FIG.
2
. The storage module is designated by the general reference character
200
, and is shown to be coupled to a command link
202
and a data link
204
. The command link
202
includes a command address bus
206
, a command clock bus
208
, and a flag line
210
. The command address bus
206
, in the particular arrangement of
FIG. 2
, carries command address signals CA
0
-CA
9
. In addition, the command clock bus
208
carries complementary command clock signals CCLK and CCLK_, and the flag line
210
that carries a flag signal FLAG. The CA
0
-CA
9
signals and FLAG signal are intended to be synchronous with the CCLK/CCLK_ signals. The signals on the command link
202
are unidirectional, being transmitted from a controller to the data storage module
200
.
The data link
204
of the particular example set forth in
FIG. 2
consists of a data bus
212
that carries signals DQ
0
-DQ
17
, an even data clock line
214
that carries an even data clock signal DCLK
0
, and an odd data clock line
216
that carries an odd data clock signal DCLK
1
. The signals on the data link
204
are bi-directional, being transmitted from a controller to the storage module
200
, or from the storage module
200
to the controller. Data on the data bus
212
are intended to be synchronous with the DCLK
0
or DCLK
1
signals, and will enable the storage module
200
to latch write data, or enable the controller to latch read data.
The storage module
200
can be considered “deeper” in that it includes a number of packet-based semiconductor memory devices
218
-
0
to
218
-x arranged in parallel. The storage module
200
includes a command address buffer
220
that receives the CCLK/CCLK_, CA
0
-CA
9
, and FLAG signals from the command link
202
. The command address buffer
220
drives the received signals on an internal module data link
222
that is commonly coupled to the memory devices (
218
-
0
to
218
-x). The storage module
200
also includes a data buffer
224
that is connected between the data link
204
and an internal module data link
226
. The module data link
226
is commonly connected to the memory devices (
218
-
0
to
218
-x). The data buffer
224
is a two-way buffer, buffering data signals (DQ
0
-DQ
17
) and data clock signals (DCLK
0
and DCLK
1
) from the memory devices (
218
-
0
to
218
-x) to the controller, as well as from the controller to the memory devices (
218
-
0
to
218
-x).
To better understand the timing associated with the prior art packet-based data storage system set forth in
FIGS. 1 and 2
, two timing diagrams are provided in
FIGS. 3A and 3B
.
FIG. 3A
sets forth an idealized version of command/address timing issued from a controller to the data storage module
200
.
FIG. 3A
is shown to include the command clock signal CCLK, the FLAG signal, and the CA
0
-CA
9
signals. The CCLK signal is shown to be a free running periodic clock signal. The FLAG signal is used to indicate that a command address information packet is being transmitted. As shown in
FIG. 3A
, as the FLAG signal transitions high, the CA
0
-CA
9
signals will present a first packet data field P
0
. On the subsequent CCLK cycle periods, three more packet data fields (P
1
-P
3
) are provided by the CA
0
-CA
9
signals.
FIG. 3B
sets forth an idealized version of data timing. Set forth in
FIG. 3B
is a data clock signal DCLKx and the DATA signals DQ
0
-DQ
17
. The DCLKx signal may be either the DCLK
0
signal or DCLK
1
signal. The data timing set forth in
FIG. 3B
can be considered to represent a data write operation or a data read operation, as in both cases, data presented on bus DQ
0
-DQ
17
will be accompanied by a DCLKx signal. The DCLKx signal is ideally synchronous with (but not necessarily in exact phase with) the CCLK signal. Prior to time t
0
, the DCLKx signal is in a high impedance state. Other circuitry on the data bus (not shown) such as termination devices maintain the DCLKx signal at an intermediate logic value.
At time t
0
, the DCLKx signal begins a “preamble” which precedes the transmission of data on the data bus (DQ
0
-DQl
7
). If the preamble is considered in terms of half cycles (“ticks”) it is shown to have a value of “00010.” Following the preamble, a burst of data (D
0
-D
3
) is driven on the data bus (DQ
0
-DQ
17
).
A drawback to the prior art approaches set forth and illustrated in
FIGS. 1
,
2
,
3
A and
3
B, can arise when deeper data storage modules are used in the system. Due to the capacitance and resistance of the controller command link
202
and the module command link
222
, command and address information, as well as the command clocks (CCLK/CCLK_), can be degraded. Even the use of a command address buffer
220
and data buffer
224
may still result in signal degradation, as the buffers (
220
and
224
) can pass on the degraded signals between the storage module
200
and its associated command link
202
and data link
204
. This can particularly true if the degradation is an unwanted phase difference between the d
Brady III Wade James
Kim Matthew
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tzeng Fred F.
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