Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-02-22
2005-02-22
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S011000
Reexamination Certificate
active
06859892
ABSTRACT:
A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.
REFERENCES:
patent: 6263452 (2001-07-01), Jewett et al.
patent: 6279119 (2001-08-01), Bissett et al.
patent: 6598178 (2003-07-01), Yee et al.
patent: 6694449 (2004-02-01), Ghameshlu et al.
patent: 6708326 (2004-03-01), Bhattacarya
Bolding Joe
Everett Gerald
Tormey Dan
Bonura Timothy M.
Hewlett--Packard Development Company, L.P.
Iqbal Nadeem
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