Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1996-07-29
2002-04-09
Courtenay, III, St. John (Department: 2151)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S601000
Reexamination Certificate
active
06370651
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to the field of integrated circuit memory devices. More particularly, this invention relates to synchronizing user commands for an array controller in a memory device.
2. Art Background
A flash memory device implements a flash cell array for non-volatile random access data storage for a computer system. A typical prior flash memory device implements a write control circuit for performing program and erase options on areas of the flash cell array. Such a write control circuit typically programs flash cells by applying a predetermined sequence of program level voltages to the flash cells.
Typically, a user provides an input/output driver program that issues user commands to the flash memory device. The user commands commonly include commands for programming and erasing portions of the flash cell array. The write control circuit usually receives and verifies the user commands and performs the functions specified to program or erase an area of the flash cell array.
A flash memory device may implement a specialized micro controller for performing program and erase algorithms on the flash cell array. Such a specialized micro controller is typically driven by an oscillator circuit. The oscillator circuit generates the necessary clock signals to synchronize the operation of the micro controller.
In such systems, the oscillator circuit can be disabled after the micro controller executes a user command and shuts down. The disabled oscillator circuit halts the micro controller and reduces power consumption of the flash memory device. The oscillator circuit is then re-enabled when a subsequent user command is received. The micro controller restarts and performs the program or erase operation specified by the subsequent user command.
The user commands transferred to the flash memory device are usually not synchronized to the micro controller. The user commands are usually transferred to the flash memory device over a host bus, and are typically synchronized by a write enable signal on a control portion of the host bus. The timing of the write enable signal usually has no relation to the timing generated by the oscillator circuit.
As a consequence, a race condition can exist when the flash memory device receives the subsequent user command during a shut down sequence after execution of the previous user command. The subsequent user command could re-enable the oscillator circuit and restart the micro controller during shut down. Such a premature re-enable of the oscillator circuit could cause a partial reset of the micro controller. The partial reset could cause the micro controller to restart in an unknown state.
SUMMARY AND OBJECTS OF THE INVENTION
One object of the present invention is to synchronize the start-up and shut down sequences of a micro controller in a flash memory device during transfer of user commands to the flash memory device.
Another object of the present invention is to coordinate the start-up and shut down sequences of the micro controller such that a user command received during shut down does not cause a partial reset of the micro controller.
Another object of the present invention is to shut down the micro controller and disable an oscillator circuit for the micro controller if a user command specifying an operation on a flash cell array in the flash memory device is not pending.
A further object of the present invention is to shut down the micro controller and disable an oscillator circuit if a user command is not pending in a temporary queue or an operation queue to the micro controller.
These and other objects of the invention are provided by a method and apparatus for synchronizing a micro controller in a flash memory device. An interface circuit receives a user command over a host bus, and stores the user command in an operation queue to the micro controller. A synchronizer circuit enables an oscillator circuit if the user command specifies an operation on a flash cell array. The oscillator circuit generates a clock signal for the micro controller.
The synchronizer circuit receives a halt signal from the micro controller. The halt signal indicates that the operation is complete. The synchronizer circuit then disables the oscillator circuit if a subsequent user command that specifies a subsequent operation for the micro controller is not pending.
Other objects, features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description that follows below.
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Durante Richard J.
Fandrich Mickey L.
Rozman Rodney R.
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