Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-02-11
2008-08-26
Bonzo, Bryce P. (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
07418629
ABSTRACT:
A method, apparatus, and computer program product are disclosed in a data processing system for synchronizing the triggering of multiple hardware trace facilities using an existing bus. The multiple hardware trace facilities include a first hardware trace facility and a second hardware trace facility. The data processing system includes a first processor that includes the first hardware trace facility and first processing units that are coupled together utilizing the system bus, and a second processor that includes the second hardware trace facility and second processing units that are coupled together utilizing the system bus. Information is transmitted among the first and second processing units utilizing the system bus when the processors are in a normal, non-tracing mode, where the information is formatted according to a standard system bus protocol. Trigger events are transmitted to the hardware trace facilities utilizing the same standard system bus, where the trigger events are also formatted according to the standard system bus protocol.
REFERENCES:
patent: 4590550 (1986-05-01), Eilert et al.
patent: 4835675 (1989-05-01), Kawai
patent: 5206948 (1993-04-01), De Angelis et al.
patent: 5210862 (1993-05-01), DeAngelis et al.
patent: 5642478 (1997-06-01), Chen et al.
patent: 5890217 (1999-03-01), Kabemoto et al.
patent: 6134676 (2000-10-01), VanHuben et al.
patent: 6857083 (2005-02-01), Floyd et al.
patent: 6912673 (2005-06-01), Wyland
patent: 7080289 (2006-07-01), Swaine et al.
patent: 7152186 (2006-12-01), Airaud et al.
patent: 7200776 (2007-04-01), Harris
patent: 7213169 (2007-05-01), Dodson et al.
patent: 7269756 (2007-09-01), Baartmans et al.
patent: 2003/0196141 (2003-10-01), Shaw
patent: 2004/0019828 (2004-01-01), Gergen et al.
patent: 2004/0199823 (2004-10-01), Dodson et al.
patent: 2005/0268171 (2005-12-01), House et al.
patent: 2006/0184835 (2006-08-01), Al-Omari et al.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Performing In-Memory Tracing Using Existing Communication Paths, filed Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Concurrently Sharing a Memory Controller Among a Tracing Process and Non-Tracing Processes Using a Programmable Variable Number of Shared Memory Write Buffers, filed Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Dynamically During Runtime Allocating Memory for In-Memory Hardware Tracing, filed Feb. 11, 2005.
Al-Omari et al., Method, Apparatus, and Computer Program Product in a Processor for Balancing Hardware Trace Collection Among Different Hardware Trace Facilities, filed Feb. 11, 2005.
Al-Omari Ra'ed Mohammad
Floyd Michael Stephen
Lecocq Paul Frank
Bonzo Bryce P.
Gerhardt Diana R.
International Business Machines - Corporation
Manzo Peter B.
Miles Neil D
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