Synchronizing processors when entering system management mode

Details Synchronizing processors when entering system management mode Synchronizing processors when entering system management mode

2011-08-02

2011-08-02

Stiglic, Ryan M (Department: 2111)

Electrical computers and digital data processing systems: input/

Interrupt processing

Multimode interrupt processing

C710S267000, C713S375000

Reexamination Certificate

active

07991933

ABSTRACT:
A system to synchronize processors includes one or more subsystems to receive an interrupt command, instruct a plurality of processors to enter an entry synchronization loop of an interrupt handler, determine by each of the plurality of processors whether all of the plurality of processors have entered their respective interrupt handler before exiting the entry synchronization loop, determine whether a timeout value has been reached, determine type of the interrupt command received and in response to the type of interrupt command received, and determine whether to exit the entry synchronization loop after the timeout value has been reached.

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