Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2008-07-01
2008-07-01
Tse, Young T. (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S376000, C711S149000, C711S209000
Reexamination Certificate
active
07394884
ABSTRACT:
To synchronize a regularly occurring pulse train to the average of a bunched pulse train, an oscillator generates a plurality of differently phase shifted signals at a given frequency. One of the phase shifted signals is selected as an output signal. The output signal is compared with the bunched pulse train. The selected phase shifted signal is changed responsive to the comparison so the output signal occurs at the average frequency of the bunched pulse train. The oscillator is formed as a plurality of differential amplifier stages having equal controllable delays. The stages are connected together to form a ring oscillator. The output signal is compared with the bunched pulse train through a FIFO. A signal representative of the state of the FIFO is used as an error signal to control the selection of the phase shifted signal to be used as the output signal. A phase locked loop that synchronizes the phase shifted signal generating oscillator to a frequency reference is nested in the control loop that selects one of the phase shifted signals as the output signal.
REFERENCES:
patent: 4353099 (1982-10-01), Shum et al.
patent: 4596026 (1986-06-01), Cease et al.
patent: 4941156 (1990-07-01), Stern et al.
patent: 5142555 (1992-08-01), Whiteside
patent: 5410723 (1995-04-01), Schmidt
patent: 5493243 (1996-02-01), Ghoshal
patent: 5600379 (1997-02-01), Wagner
patent: 5602882 (1997-02-01), Co et al.
patent: 5604741 (1997-02-01), Samueli et al.
patent: 5793824 (1998-08-01), Burch et al.
patent: 5844436 (1998-12-01), Altmann
patent: 5956748 (1999-09-01), New
patent: 6033441 (2000-03-01), Herbert
patent: 6081844 (2000-06-01), Nowatzyk et al.
patent: 6118835 (2000-09-01), Barakat et al.
patent: 6226698 (2001-05-01), Yeung et al.
patent: 6278718 (2001-08-01), Eschholz
patent: 6421770 (2002-07-01), Huch et al.
patent: 6463111 (2002-10-01), Upp
D. Chen, “A Power and Area Efficient CMOS Clock/Data Recovery Circuit for High-Speed Serial Interfaces”, IEEE Journal of Solid-State Circuits, vol. 31, No. 8, Aug. 8, 1996, pp. 1170-1176, New York.
D. Chen et al., “A Single-Chip 266Mb/s CMOS Transmitter/Receiver for Serial Data Communications”, Circuits Conference; Digest of Technical Papers; 40thISSCC; IEEE International, 1993, pp. 100-101, 269.
“Hybrid Analog/Digital Clock Recovery for Burst-Mode-Data”, IBM Technical Disclosure Bulletin, US, IBM Corp., New York, vol. 37, No. 4B, Apr. 1994, pp. 407-408.
Kaylani Tarek
Lu Fang
Samueli Henry
Broadcom Corporation
Sterne Kessler Goldstein & Fox PLLC
Tse Young T.
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