Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
1999-12-06
2003-04-29
Lee, Thomas (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C710S057000, C710S058000
Reexamination Certificate
active
06557109
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a synchronizing device and a synchronizing method. More to particularly this invention relates to a synchronizing device and a synchronizing method in a transmission system which uses MPEG (Moving Picture Experts Group) and so forth.
DESCRIPTION OF THE PRIOR ART
Generally, in a transmission system such as broadcasting and so forth using the MPEG standard, timing of regeneration of data in the reception side is necessarily synchronized with the sending side. This is because if the timing of regeneration is too fast, the reception side will have insufficient data (underflow). Conversely, if the timing of regeneration is too slow, the reception side will have too much data (overflow). Hence, synchronizing devices are used to cause the timing of the reception side to be synchronized with the timing of the sending side.
Formerly, the synchronizing device described in “Point Pictorial System The Newest MPEG Text Book” (author, supervision: Hiroshi Fujiwara, editor: Society for the Study of Multi-Media Communication) pp. 237, Aug. 1, 1994, is well known. This synchronizing device is generally designated as PLL (Phase Locked Loop) circuit. As shown in
FIG. 1
, the synchronizing device comprises a Digital Analog Converter DAC
201
, a Low Pass Filter LPF
202
, a Voltage Control Oscillator VCO
203
, System Time Clock STC
204
(synchronous signal counter), and a subtracter
205
. The output of the Digital Analog Converter
201
controls frequency of a clock signal which the Voltage Control Oscillator
203
oscillates through the Low Pass Filter
202
. The clock signal which the Voltage Control Oscillator
203
outputs is counted by the System Time Clock
204
to be inputted to the subtracter
205
. It is obtained difference between System Clock Reference (SCR) or Program Clock Reference (PCR) included in the MPED data and the value of the System Time Clock (STC)
204
by the subtracter
205
, thus being inputted to the Digital Analog Converter (DAC)
201
. The difference converted into the analog value is inputted to the Voltage Control Oscillator (VCO)
203
through the Low Pass Filter (LPF)
202
. The Voltage Control Oscillator (VCO)
203
changes the frequency of the clock signal which oscillates in accordance with value of difference. For instance, when the value of the System Clock Reference (SCR) or the value of the Program Clock Reference (PCR) is larger than the value of the System Time Clock (STC)
204
, the frequency of the clock signal which the Voltage Control Oscillator (VCO)
203
oscillates changes in the direction that the frequency becomes large. To the contrary, when the value of the System Clock Reference (SCR) or the value of the Program Clock Reference (PCR) is smaller than the value of the System Time Clock (STC)
204
, the frequency of the clock signal which the Voltage Control Oscillator (VCO)
203
oscillates changes in the direction that the frequency becomes small. According to the operation, the synchronizing device generates clock signal synchronized with sending side of the data. The regeneration circuit of the MPEG data is capable of executing regeneration synchronized with the sending side in such a way that the regeneration circuit of the MPEG data regenerates the clock signal synchronized with the sending side as the reference clock signal.
However, in the conventional synchronizing device, analog devices such as the Low Pass Filter (LPF), the Voltage Control Oscillator: (VCO), and so forth are used. Since characteristics of these analog devices are easily changed by variations in temperature and power source voltage, it is difficult to stabilize operation of the device.
Further, in the conventional synchronizing device, the clock of 27 MHz is necessary for the MPEG. The processing that it achieves synchronization with frequency of the clock changed delicately while referring to the value of the System Clock Reference (SCR) or the value of the Program Clock Reference (PCR), is incapable of being realized by the CPU of the personal computer which is used generally, therefore, there is the problem that it is difficult to be realized by software.
SUMMARY OF THE INVENTION
In view of the foregoing, it is an object of the present invention, in order to overcome the above-mentioned problems, to provide a synchronizing device and a synchronizing method whose constitution is simple, and whose operation is easily stabilized.
It is another object of the present invention, to provide a synchronizing device and a synchronizing method which is easily realized by software.
According to a first aspect of the present invention, in order to achieve the above-mentioned objects, there is provided a synchronizing device which comprises a memory device for storing therein data temporarily, a data reading-out means for reading data of the memory device, a data remaining quantity detection means for detecting remaining quantity of the data of the memory device, and a data reading-out speed control means for causing remaining quantity of the data of the memory device to be prescribed value while controlling data reading-out speed of the data reading-out means based on detection data remaining quantity detected by the data remaining quantity detection means.
According to a second aspect of the present invention, in the first aspect, there is provided a synchronizing device, wherein the data remaining quantity detection means of the synchronizing device comprises a write pointer for calculating number of data written in the memory device, a read pointer for calculating number of data read from the memory device, and a subtracter for subtracting value of the read pointer from value of the write pointer to obtain subtraction value before giving it to the data reading-out speed control means with the subtraction value as the detection data remaining quantity.
According to a third aspect of the present invention, there is provided a synchronizing device which comprises a memory device for storing therein data temporarily, a data reading-out means for reading data of the memory device a data remaining quantity detection means for detecting remaining quantity of the data of the memory device, a decoder for receiving data read-out from the data reading-out means, a number of data increasing/decreasing unit for receiving data from the decoder, and a data reading-out speed control means for causing remaining quantity of data of the memory device to be prescribed value while controlling data reading-out speed of the data reading-out means in such a way that it controls quantity of data outputted from the number of data increasing/decreasing unit based on detection data remaining quantity detected by the data remaining quantity detection means.
According to a fourth aspect of the present invention, in the third aspect, there is provided a synchronizing device, wherein the data remaining quantity detection means comprises a write pointer for calculating number of data written in the memory device, a read pointer for calculating number of data read from the memory device, and a subtracter for subtracting value of the read pointer from value of the write pointer to obtain subtraction value before giving it to the data reading-out speed control means with the subtraction value as the detection data remaining quantity.
According to a fifth aspect of the present invention, there is provided a synchronizing method which comprises the steps of a storing step for storing data temporarily according to a memory device, a data reading-out step for reading data of the memory device by data reading-out means, a data remaining quantity detecting step for detecting remaining quantity of data of the memory device, and a data reading-out speed controlling step for causing remaining quantity of the memory device to be prescribed value while controlling data reading-out speed of the data reading-out means based on detection data remaining quantity detected by the data remaining quantity detecting step.
According to a sixth aspect of the present i
Lee Thomas
NEC Corporation
Wang Albert
Whitham Curtis & Christofferson, P.C.
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