Synchronizing control and data paths traversed by a data...

Details Synchronizing control and data paths traversed by a data... Synchronizing control and data paths traversed by a data...

2006-06-23

2010-11-16

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

Reexamination Certificate

active

07836229

ABSTRACT:
In one embodiment, the present invention includes a method for determining if control and data portions of a data transaction are ready to be sent from an interface coupled to a processor core. If so, the data portion may be sent from an entry of a data buffer of the interface, and the entry deallocated. Furthermore, a value corresponding to the deallocated entry may be written in multiple buffers of the interface. In this way, independent paths of the interface may be synchronized. Other embodiments are described and claimed.

REFERENCES:
patent: 6009488 (1999-12-01), Kavipurapu
patent: 6385695 (2002-05-01), Arimilli et al.
patent: 7239645 (2007-07-01), Suri et al.
patent: 2005/0223177 (2005-10-01), Pentkovksi et al.
patent: 2007/0050564 (2007-03-01), Gunna et al.

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