Synchronizing circuit

Details Synchronizing circuit Synchronizing circuit

1990-10-03

1992-11-10

Olms, Douglas W.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

370106, 375120, H04N 504, H03L 700

Patent

active

051629100

ABSTRACT:
A phase locked loop circuit regenerates a synchronizing signal. A first counter counts adjustable and fixed time intervals. A flip/flop generates synchronizing pulses having periods defined by sets of the adjustable and fixed time intervals. A second counter successively measures phase differences between synchronizing pulses and input pulses related to a synchronizing component in a video signal. The phase differences are measured between the ends of the adjustable time intervals in the synchronizing pulses and the input pulses. Each of the phase measurements results in a period correction value for controlling the duration or period of the very next one of the adjustable time intervals. The second counter is reset at the ends of the fixed time intervals. A network defining a loop filter may comprise an accumulator, a first scaler, a summer, and a second scaler for calculating weighted phase difference measurements to define the period correction values. A multiplexer responsive to the synchronizing pulses selects between the period correction values and a constant value as an output value for determining when the first counter is reset.

REFERENCES:
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4360926 (1982-11-01), Hedin et al.
patent: 4380742 (1983-04-01), Hart
patent: 4396991 (1983-08-01), Baldwin et al.
patent: 4400664 (1983-08-01), Moore
patent: 4462110 (1984-07-01), Baldwin et al.
patent: 4466111 (1984-08-01), Bennett
patent: 4471299 (1984-09-01), Elmis
patent: 4488170 (1984-12-01), Nillesen
patent: 4504799 (1985-03-01), Elmis et al.
patent: 4636861 (1987-01-01), Willis
patent: 4639780 (1987-01-01), Willis
patent: 4680780 (1987-07-01), Agoston et al.
patent: 4763342 (1988-08-01), Ambrosio et al.
patent: 4769704 (1988-09-01), Hirai et al.
patent: 4769705 (1988-09-01), Lendaro
IBM Technical Disclosure Bulletin, vol. 13, No. 7, 7 Dec. 1970, pp. 1863-1864, "Phase Locked Loop With Delay Line Oscillator", by Laurich et al.

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