Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-10-12
1996-06-18
Tse, Young T.
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375355, 375362, 327161, H04L 702
Patent
active
055286372
ABSTRACT:
A synchronizing circuit (SC) is proposed which recovers from input data (ID) applied thereto a data clock signal (DC) synchronous therewith in frequency and in phase. The circuit (SC) consists of a tuned tapped delay line (TDL) generating a plurality of mutually delayed local clock signals (DCS), a latching circuit (SM) sampling these delayed local clock signals at input data level transitions thereby providing sampled versions (LCSV) thereof as well as a comparator (C1) pairwise comparing said delayed local clock signals with respective ones of the sampled versions. It can be verified that with such a circuit the level transitions of the appropriate data clock signal (DC) are generated at the outputs of the comparator (C1) when the latter drives its output high only if a sufficient number of its pairwise comparisons hold.
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Naert Hans A. M.
Sevenhans Joannes M. J.
ALCATEL N.V.
Tse Young T.
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