Synchronizing a translation lookaside buffer to an extended...

Details Synchronizing a translation lookaside buffer to an extended... Synchronizing a translation lookaside buffer to an extended...

2006-08-15

2009-06-30

Lane, Jack A (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S203000, C711S207000, C711S208000, C711S209000

Reexamination Certificate

active

07555628

ABSTRACT:
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

REFERENCES:
patent: 6430670 (2002-08-01), Bryg et al.
patent: 2008/0082772 (2008-04-01), Savagaonkar et al.
patent: 1681630 (2006-07-01), None
patent: WO-9211597 (1992-07-01), None
patent: WO-2006081582 (2006-08-01), None
Advanced Micro Devices; “AMD64 Virtualization Codenamed “Pacific” Technology”; Secure Virtual Machine Architecture Reference Manual; pp. 49-51; http://enterprise.amd.com/downloadables/Pacifica—spec.pdf.
IBM System/370 Extended Architecture; Interpretive Execution; Publication No. SA22-7095-1; File No. S370-01, Sep. 1985.
“Combined Search and Examination Report for UK Application No. GB0715604.5”, (Dec. 10, 2007), 8 pgs.

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