Synchronizing a plurality of processors

Details Synchronizing a plurality of processors Synchronizing a plurality of processors

2007-01-11

2009-06-23

Auve, Glenn A (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C713S375000

Reexamination Certificate

active

07552269

ABSTRACT:
In a first aspect, a first method of synchronizing a plurality of processors of a system is provided. The first method includes the steps of (1) modifying a peripheral component interconnect express (PCIe) protocol to include a completion status encode associated with a synchronization command that indicates whether a condition of the synchronization command is met; (2) providing a system including (a) a memory; (b) a first processor coupled to the memory; (c) a second processor; and (d) an interconnect coupling the second processor to the first processor and the memory; and (3) employing the modified PCIe protocol on the interconnect. Numerous other aspects are provided.

REFERENCES:
patent: 7454551 (2008-11-01), Myers
patent: 2005/0120163 (2005-06-01), Chou et al.
patent: 2006/0179255 (2006-08-01), Yamazaki
patent: 2006/0277347 (2006-12-01), Ashmore et al.
patent: 2008/0112313 (2008-05-01), Terakawa

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