Synchronized data processing system and image processing system

Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit

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345507, 345514, 713500, G09G 536

Patent

active

059991976

ABSTRACT:
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules coupled to said bus control circuit for producing data and addresses for accessing a memory; and a clock driver for feeding intrinsic operation clocks to said data processing modules and for feeding the clock signal for accessing said memory in synchronism with the operations of said data processing modules to be operated by the operation clock signals, to the outside.

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