Synchronization technique for high speed memory subsystem

Details Synchronization technique for high speed memory subsystem Synchronization technique for high speed memory subsystem

2003-02-06

2008-12-23

Sough, Hyung (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S159000

Reexamination Certificate

active

07469328

ABSTRACT:
A technique synchronizes data retrieved from memory devices at a memory controller of a high-speed memory subsystem. Each memory device is organized into a plurality of data groupings. The memory controller stores (via one or more write operations) a known synchronization (sync) pattern at each data grouping on the memory devices and then retrieves (via one or more read operations) that sync pattern from the groupings. Synchronization logic located at a local clock boundary of the memory controller is configured to recognize the retrieved sync pattern and “automatically” synchronize all pieces of data retrieved from the data groupings, even though there may be substantial skew between the groupings.

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