Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1997-12-24
2001-01-23
Pham, Chi H. (Department: 2731)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C455S260000, C375S362000
Reexamination Certificate
active
06178215
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to network clock reference synchronization.
BACKGROUND OF THE INVENTION
Many networks require strict synchronization (Sync) between network elements for proper performance. For example, digital wireless communication systems (cellular or PCS), referred to below as wireless systems, are dependent upon strict synchronization between the base station system (BSS); terminals, e.g., mobile handsets or mobile stations (MS); and other network elements. The BSS system typically includes a base station controller (BSC) and multiple base transceiver stations (BTS).
If sufficient synchronization is not obtained in the BTS or the BSC, the quality of the communication links can be compromised. As example of the importance of synchronization, it has been found that the speed of handover or handoff operation, the call drop rate, and the link quality, of a mobile system are directly or indirectly dependent upon the performance of the system synchronization. Cellular or PCS radio system performance is significantly restrained by its systems synchronization in two aspects:
i) phase accuracy, and
ii) frequency accuracy.
With respect to aspect (i), improving phase accuracy (ie., reducing phase differences between the recovered clock and the local synchronization module output clock) will result in a lower frame slipping rate at the BTS network interface, and thus better traffic link quality.
With respect to aspect (ii), improving the frequency accuracy of the local synchronization module output clock will result in faster handovers, lower handover and camping-in call block rates, and lower radio system interference levels. Thus, both of these 2 aspects are important for obtaining desirable link quality and systems performance. Note that as well as the accuracy, the stability of the signal is also important.
For the purpose of synchronisation, in each BTS and BSC, a synchronisation module is required and defined in various of radio technologies (such as GSM, CDMA and TDMA). For example, for GSM, the synchronisation in each BTS is required as:
“The BTS shall use a single frequency source of absolute accuracy better than 0.05 PPM for both RF frequency generation and clocking time base. The same source shall be used for all carriers of the BTS.”
There are three basic methods to implement the synchronisation:
1. GPS method: Put a global positioning system (GPS) receiver in each of BTSs and BSCs;
2. Fixed frequency method: Use a very accurate and fixed frequency source, for example an oven-controlled crystal oscillator (OCXO) in each of BTSs and BSCs for the independent clock source;
3. Local Sync module method: Use a stable controllable crystal oscillator such as an oven-controlled voltage-controlled crystal oscillator (OCVCXO) to implement either a phase locked loop (PLL) or a frequency locked loop (FLL) in each of BTSs and BSCs so that the locally generated reference is locked (either in phase or frequency) to the public switched telephone network (PSTN) network clock source.
Using a GPS receiver has a very high cost and is generally limited to outdoor mobile systems due to the need for an antenna which can receive GPS satellite transmissions.
Using a very stable and accurate OCXO as an independent clock source in each BTS and BSC is also costly and requires a regular tuning step (once per year or per two years). Such a tuning step typically requires sending a technician to each module, which is inconvenient and costly.
Thus the third method is preferable from a cost and maintenance requirement. However, it is typically less accurate than the other two methods as it is difficult to achieve an accurate lock (either in phase or frequency) to the PSTN reference. Furthermore, even if the locally generated reference is accurately locked to the network, this does not necessarily provide a sufficiently accurate reference as the PSTN reference clock may itself drift over time. The clock recovered from the PSTN suffers phase and frequency variations or drifts caused by multiple factors, for example, jitters, wanders, phase transients, VT (virtual tributary) transients, high level clock source switchovers, high level clock module holdover, free running, etc. Thus, in practice this third method has until now been seen as a compromise between the cost and the synchronisation quality (accuracy and stability).
As stated, prior art solutions use either a PLL or an FLL to lock the local reference to the PSTN reference in either phase or frequency. A PLL is effective with respect to aspect i). However, such a PLL can lock in phase, but tends to result in a frequency drift.
In some situations, a locally generated reference which is phase locked to the network in the local synchronisation module suffers sufficient frequency drift that the frequency stability and accuracy (in the BTS or BSC) will fail to meet the radio specification requirement.
However, if a FLL is used to achieve aspect (ii), the phase tends to drift. This tends to result in increased frame slipping, and thus decreases the traffic link quality.
Thus, there exists a need for a synchronisation module which can locally generate a reference signal which overcomes these and other problems.
SUMMARY OF THE INVENTION
An aspect of this invention provides an improved local synchronisation system which uses a feed-back loop to control a controllable signal source, such as an OCVCXO, such that signal differences between the local signal and a reference signal are controlled both with respect to frequency and phase.
Another aspect of this invention provides an improved local synchronisation system which has multiple modes of operation. The multiple mode of operations include initialization, FLL, PLL, and open loop modes, wherein each mode of operation has a series of boundary conditions for adjusting between modes.
Another aspect of this invention provides an improved local synchronisation system which uses multiple boundary conditions to control both the phase and frequency characteristics.
Another aspect of this invention provides an improved local synchronisation system which controls phase errors in order to minimize slipping.
Another aspect of this invention provides an improved local synchronisation system which compensates for aging affects of said controllable signal source.
Another aspect of this invention provides an improved local synchronisation system an improved local synchronisation system which uses a Frequency-Phase Adaptive Double Locked Loop (FPADLL) to control both the phase and frequency characteristics.
In a preferred embodiment of the invention, the Sync system does not physically include a double lock loop which simultaneously locks both the phase and frequency of the stable OCVCXO reference clock. Rather, a single physical feedback loop is implemented which can operate in multiple modes of operation, for example, either a phase locked loop mode or a frequency locked loop mode. The Sync system includes a controller which determines in which mode the feedback loop operates.
Another aspect of the invention is generally applicable to sync systems which control a locally controllable oscillator by means of a feed back loop (eg. a phase lock loop or a frequency lock loop) and a reference signal. In general, such a feed back loop continuously compensates for variations in the output characteristics (e.g., frequency or phase) of the oscillator by locking either the frequency or phase of the oscillator output to that of the reference signal. Typically the variations in the output characteristics of oscillator are due to long term changes in the OCVCXO characteristics due to such environmental conditions as temperature, humidity, pressure and power supply variations (hereafter referred to as aging).
However, such a system will fail to compensate for oscillator drift in the event that the system fails to recover a suitable reference signal (either because the input is lost or becomes inaccurate/unstable, or due to some system failure, for example a failure in the recovery unit itself). Therefore,
Ferland Roger
Oprea Dan
Smith Roland
Zhang Genzao
Bayard Emmanuel
Measures Jeff
Nortel Networks Limited
Pham Chi H.
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