Synchronization of weakly ordered write combining operations usi

Details Synchronization of weakly ordered write combining operations usi Synchronization of weakly ordered write combining operations usi

1998-03-31

2000-06-06

Lane, Jack A.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711167, G06F 1314, G06F 1200

Patent

active

060732105

ABSTRACT:
The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.

REFERENCES:
patent: 5751996 (1998-05-01), Glew et al.
patent: 5826109 (1998-10-01), Abramson et al.
patent: 5881262 (1999-03-01), Abramson et al.
patent: 5900020 (1999-05-01), Safranek et al.

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