Synchronization of programmable multiplexers and demultiplexers

Details Synchronization of programmable multiplexers and demultiplexers Synchronization of programmable multiplexers and demultiplexers

2006-09-19

2006-09-19

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S038000, C326S093000

Reexamination Certificate

active

07109754

ABSTRACT:
Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.

REFERENCES:
patent: 5675808 (1997-10-01), Gulick
patent: 5869979 (1999-02-01), Bocchino
patent: 6000051 (1999-12-01), Nadeau-Dostie et al.
patent: 6133750 (2000-10-01), Chan
patent: 6472904 (2002-10-01), Andrews
patent: 6567943 (2003-05-01), Barnhart et al.
patent: 6744289 (2004-06-01), Nguyen

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