Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2005-02-15
2005-02-15
Le, Don (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S046000
Reexamination Certificate
active
06856171
ABSTRACT:
Systems and methods are disclosed to provide clock and data synchronization for input/output interfaces of a programmable logic device. In accordance with one embodiment, a phase-locked loop or a delay-locked loop is employed to synchronize signals for input/output circuitry. In accordance with another embodiment, a clock divider along with an edge clock distribution scheme is employed to distribute clock and reset signals for input/output circuitry.
REFERENCES:
patent: 5675808 (1997-10-01), Gulick et al.
patent: 6133750 (2000-10-01), Chan et al.
patent: 6744289 (2004-06-01), Nguyen et al.
Lattice Semiconductor Corporation
Le Don
MacPherson Kwok & Chen & Heid LLP
Michelsor Greg J.
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