Synchronization of clock signals in a multi-clock domain

Details Synchronization of clock signals in a multi-clock domain Synchronization of clock signals in a multi-clock domain

2006-05-09

2006-05-09

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S094000, C326S096000, C327S141000

Reexamination Certificate

active

07042250

ABSTRACT:
A synchronizer circuit which synchronizes an input clock signal to a sampling clock to generate a synchronized signal. In an embodiment, an adaptive module detects the occurrence of a positive edge in an input clock signal after a logic low corresponding to a prior negative edge is propagated to as a synchronized signal, and provides a logic high as an input to a sampling module. The sampling module propagates the signal led at the input as the synchronized signal. The adaptive module causing the input to remain at logic high at least until the synchronization module provides logic level as the synchronized signal. The negative edges in the input signal may also be processed similarly.

REFERENCES:
patent: 2003/0107407 (2003-06-01), Aikawa

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