Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-12-27
2004-06-29
Le, Dieu-Minh (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S012000
Reexamination Certificate
active
06757847
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to apparatus and methods for analyzing a computer system.
2. Prior Art
The state of the art in system verification and related technologies is represented by the following documents:
[1] A. Aharon, D Goodman, M. Levinger, Y. Lichtenstein, Y. Malka, C. Metzger, M. Molcho, and G. Shurek. Test program generation for functional verification of PowerPC processors in IBM. In 32
nd
Design Automation Conference, DAC 95, pages 279-285, 1995.
[2] Y. Lichtenstein, Y. Malka, and A. Aharon. Model-based test generation for processor design verification. In Innovative Applications of Artificial Intelligence (IAAI). AAAI Press, 1994.
[3] Published European Patent Application No. 84303181.5 (Publication No. 0 628 911 A2) to International Business Machines Corporation.
[4] D. Marr, S. Thakkar and R. Zucker. Multiprocessor Validation of the Pentium Pro Microprocessor, Proceedings of the COMPCON'96
[5] J. Walter et al., Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors, Proceedings of the DAC'97 (pages: 89-94)
[6] K. Hines and G. Borriello. Dynamic Communication Models in Embedded System Co-Simulation, Proceedings of the DAC'97 (pages:395-400)
[7] M. Bauer and W. Ecker. Hardware/Software Co-Simulation in a VHDL-based Test Bench Approach, Proceedings of the DAC'97 (pages:774-779)
[8] U.S. Pat. No. 5,740,353 to Kreulen et al.
The disclosures of all publications mentioned in the specification and of the publications cited therein are hereby incorporated by reference.
SUMMARY OF THE INVENTION
The present invention seeks to provide improved apparatus and methods for system analysis.
Analysis can be understood to include verification, testing, debugging and performance analysis. The application of synchronization in system verification is now described in detail.
Hardware system verification is an integral, important activity in the development of every new computer system.
The target of system verification is to clean the design from functional errors, called bugs, before manufacturing begins. System design errors may originate from different sources: inconsistent interfaces between the system components can be the result of separate design efforts; errors may escape from the process of verifying a component of the system; other reasons exist for system errors. Overall, the target of system verification is to verify whether the design of the system complies with its specification. It is important that system verification exposes such errors before the system is manufactured, as the cost of correcting a bug after manufacturing can become very high.
One method used for hardware system verification is simulation of a system model. Each system model is composed of the designs of the system components. In addition, behavioral units may be added to the model in order to simulate the behavior of system components such as peripherals.
Verification of system behavior is achieved by simulation of test programs. System test programs are composed of the execution threads for each of the system components. These system tests can be automatically generated by an automatic test generation tool. (Documents 1 and 2 listed above in the Background section describe a test generation tool for a single processor.)
System simulation models can become very large, including: several processors, several bus bridges, memory controllers and I/O bus behaviorals. The simulation of tests on such a model is time consuming. A good verification coverage cannot be obtained by mere massive simulation of many random tests. A method for increasing the quality of system tests is to force interesting sequences of events by synchronizing between different system components. Furthermore, good coverage can be obtained by testing all possible orderings of a single set of events. This can be achieved by using the synchronization method described in this invention.
System verification is based on test-programs, which are rather complex. Compared to the test-programs used in processor verification, system test-programs require the synchronization of different, independent system components. System activity is determined by a set of distributed protocols, which exhibit a lack of central control. The sequence in which the system components interact is test-variant. Good coverage of the verification-plan is obtained by different sequence combinations. And thus, the ability to control the synchronization of the system components during a test is important for efficient system verification.
System verification may be based on automatic test-program generation. The input to an automatic test-program generation tool may comprise a list of test generation directives and the output may comprise a test-program which includes the initialization and execution directives to all system components, as well as expected results. Test synchronization should be integrated into the test generation methodology in order to utilize the productivity of design-automation tools. Furthermore, test synchronization should provide the flexibility to control the delay between the synchronized system components. Short delays increase the contentions between system activities and eventually lead to the detection of design errors.
Several methods exist for implementing synchronizations among agents. The following features are important for a preferred synchronization method:
Fast speed—As few cycles as possible between the signaling event and the pending transaction. Experience shows that the smaller the synchronization delay, the higher the chances are for resource contention. In other words, the time it takes for the waiting agent to start executing the pending transaction after the signaling event is critical to achieve tight interaction.
Generic Applicability—Usability by different types of agents, including non-initiating system components, e.g., memory controllers.
Conventional testing systems depend on the type of the component they target. There are synchronization mechanisms developed for processors, and there are techniques applicable to different behaviorals, depending on the specifics of each of them, e.g. system verification: [Documents 4 and 5 listed above in the Background sections; handshake synchronization: [Document 6]; master synchronizer: [Document 7].
The present invention seeks to provide a method for synchronization which generally achieves the shortest time possible between the signaling event and the pending transaction; and also can be used with processors, I/O devices and non-initiating system components that have access to a bus. This is an efficient, strong synchronization method for use in bus-based systems. A preferred embodiment of the present invention seeks to provide a method for synchronization by means of controlling bus arbitration. This embodiment preferably comprises a SC (synchronization controller) program.
The system of the present invention may be used during normal multi-component system operation. One preferred embodiment of the present invention comprises a technique to improve verification quality. Verification typically comprises about 50% of the design effort of a new system, resulting in costs of billions of dollars. The synchronization technique described herein targets resource contention, an area notorious for containing design bugs and very hard to simulate in random verification. One objective of a preferred embodiment of the present invention is, therefore, to make system verification efforts more efficient by targeting problem areas in a limited amount of simulation time.
A particular feature of a preferred embodiment of the present invention is that the synchronization provided thereby can be described on the architectural level but works as well at any implementation level synchronization. It can be used with generally any bus protocol that uses bus arbitration to control bus trans
Farkash Monica
Geist Danny
Gewirtzman Raanan
Holtz Karen
International Business Machines - Corporation
Le Dieu-Minh
Ludwin Richard M.
Scully Scott Murphy & Presser
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