Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2011-01-11
2011-01-11
Lee, Thomas (Department: 2116)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Reexamination Certificate
active
07870413
ABSTRACT:
A clocking scheme is provided to synchronize system clock across plural independent SMP (Symmetric Multi-Processing) domains of the multi-processor system. Each of the SMP domains is connected with another through an interconnection board and two or more identical connectors. The clocking scheme includes a clock source, a SPLL (Select Phase-Locked Loop) and a clock buffer on each of the SMP domains to provide a dedicated base clock. A self-clock path is used to send the base clock from the clock source to the SPLL on the same SMP domain, and on the other hand one or more base clock is sent through a distribution-clock path to another SPLL. The distribution-clock path and the self-clock path will have equal lengths, making the base clock pass through the two connectors or the same connector twice to achieve the similar electrical characteristics and balance the skew or propagation delay.
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Hirai Tomonori
Jong Jyh Ming
Lee Thomas
Mitac International Corp.
Rehman Mohammed H
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