Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-03-17
1998-08-11
Chin, Wellington
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375360, 327152, 327161, H04L 702
Patent
active
057938237
ABSTRACT:
It is an object to realize a synchronization circuit with small size and low consumption power which enables capturing and phasing of external data without running external clock in parallel. Internal clock (2) is delayed by a delay line (1) to produce delay clocks (3), and one of the delay clocks (3) having its rise almost corresponding to that of an external data signal (6) becomes a select clock (5). An elastic store circuit (7) is a circuit which controls a row of D-latches with a row of C elements. Thus the elastic store circuit (7) captures the external data signal (6) with enough set up hold time at timing of the select clock (5) and then outputs the captured external data as an internal data signal (8) in synchronization with the internal clock (2).
REFERENCES:
patent: 4494021 (1985-01-01), Bell et al.
patent: 5502750 (1996-03-01), Co et al.
patent: 5602882 (1997-02-01), Co et al.
IEEE Journal of Solid-State Circuits, vol. SC-22, No. 2, Apr. 1987, pp. 255-261, Deog-Kyoon Jeong, et al., "Design of PLL-Based Clock Generation Circuits".
1992, IEEE International Solid-State Circuits Conference, pp. 94-95, Mehran Bagheri, et al., "TA 5.3: 11.6GHz 1:4 Demultiplexer with Bit-Rotation Control and 6.1 GHz Auto-Latching Phase-Aligner ICS".
Kohama Shigeki
Kondoh Harufusa
Nishio Satoshi
Yoshimura Tsutomu
Chin Wellington
Luther William
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric Engineering Co. Ltd.
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