Synchronization circuit for a Viterbi decoder

Details Synchronization circuit for a Viterbi decoder Synchronization circuit for a Viterbi decoder

1983-07-06

1985-07-02

Ng, Jin F.

Pulse or digital communications

Spread spectrum

Direct sequence

371 46, H04L 704

Patent

active

045272794

ABSTRACT:
A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.

REFERENCES:
patent: 3665396 (1972-05-01), Forney, Jr.
patent: 3789359 (1974-01-01), Clark, Jr. et al.
patent: 3872432 (1975-03-01), Bismarck
patent: 4346473 (1982-08-01), Davis
patent: 4447908 (1984-05-01), Chevillat et al.
patent: 4462101 (1984-07-01), Yasuda et al.

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