Synchronization and channel deskewing circuitry for...

Details Synchronization and channel deskewing circuitry for... Synchronization and channel deskewing circuitry for...

2004-04-22

2008-11-18

Hafiz, Tariq (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C713S400000, C713S503000

Reexamination Certificate

active

07454537

ABSTRACT:
The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.

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