Symmetrical vertical lightly doped drain transistor and method o

Details Symmetrical vertical lightly doped drain transistor and method o Symmetrical vertical lightly doped drain transistor and method o

1996-10-17

1998-09-29

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257408, 257623, H01L 21336

Patent

active

058148612

ABSTRACT:
A symmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes a first region having a generally planar upper surface and a second region, projecting upwardly from the first region and having a generally planar upper surface, the second substrate region having opposed sidewalls generally normal to the upper surface of the first substrate region. A gate electrode is formed through an insulating film on the upper surface of the second substrate region, source/drain impurity regions are formed in the substrate on opposite sides of said gate electrode, and a channel region is formed under the gate electrode between the source/drain regions. Contours of equal ion concentration in the source/drain regions are non-Gaussian and an interface between the channel region and each source/drain region is generally linear beneath the gate electrode adjacent the opposing sidewalls of the second substrate region.

REFERENCES:
patent: 5041885 (1991-08-01), Gualandris et al.
patent: 5262337 (1993-11-01), Kim
patent: 5319231 (1994-06-01), Yamazaki et al.
patent: 5565700 (1996-10-01), Chou et al.
patent: 5583364 (1996-12-01), Nakamura
patent: 5640035 (1997-06-01), Sudo et al.

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