Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2011-04-05
2011-04-05
Odom, Curtis B (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S372000, C375S373000, C377S118000
Reexamination Certificate
active
07920665
ABSTRACT:
A symmetrical range controller for phase-locked loop circuits includes a first counter coupled to a first signal line, where the first counter is configured to count state transition edges of the first signal, inhibit logic coupled to the first counter, where the inhibit logic is configured to inhibit an output signal of a second counter in response to a predetermined count of the first counter, and reset logic coupled to the first counter, where the reset logic is configured to reset the second counter in response to a full count of the first counter.
REFERENCES:
patent: 4061987 (1977-12-01), Nagahama
patent: 4075569 (1978-02-01), Wright
patent: 4378509 (1983-03-01), Hatchett et al.
patent: 4492934 (1985-01-01), Sugimoto
patent: 4535459 (1985-08-01), Hogge, Jr.
patent: 4588968 (1986-05-01), Wile
patent: 4593254 (1986-06-01), Coburn
patent: 4594564 (1986-06-01), Yarborough, Jr.
patent: 4617678 (1986-10-01), Devensky et al.
patent: 4773085 (1988-09-01), Cordell
patent: 4787097 (1988-11-01), Rizzo
patent: 4855683 (1989-08-01), Troudet et al.
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 4940952 (1990-07-01), Kegasa
patent: 4943788 (1990-07-01), Laws et al.
patent: 5003599 (1991-03-01), Landry
patent: 5005191 (1991-04-01), O'Connor
patent: 5010559 (1991-04-01), O'Connor
patent: 5022056 (1991-06-01), Henderson et al.
patent: 5101203 (1992-03-01), Gersbach et al.
patent: 5120990 (1992-06-01), Koker
patent: 5138281 (1992-08-01), Boudewijns
patent: 5175767 (1992-12-01), Landry
patent: 5197086 (1993-03-01), Jackson et al.
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5367544 (1994-11-01), Bruekheimer
patent: 5384551 (1995-01-01), Kennedy et al.
patent: 5418497 (1995-05-01), Martin
patent: 5436938 (1995-07-01), Pigeon
patent: 5487093 (1996-01-01), Adresen et al.
patent: 5506875 (1996-04-01), Nuckolls et al.
patent: 5512860 (1996-04-01), Huscroft et al.
patent: 5539345 (1996-07-01), Hawkins
patent: 5548251 (1996-08-01), Chou et al.
patent: 5574756 (1996-11-01), Jeong
patent: 5598424 (1997-01-01), Erickson et al.
patent: 5608734 (1997-03-01), Sandler et al.
patent: 5614855 (1997-03-01), Lee et al.
patent: 5652531 (1997-07-01), Co et al.
patent: 5661763 (1997-08-01), Sands
patent: 5663665 (1997-09-01), Wang et al.
patent: 5666547 (1997-09-01), James et al.
patent: 5671223 (1997-09-01), Shachar et al.
patent: 5694056 (1997-12-01), Mahoney et al.
patent: 5694088 (1997-12-01), Dickson
patent: 5712580 (1998-01-01), Baumgartner et al.
patent: 5719908 (1998-02-01), Greeff et al.
patent: 5731723 (1998-03-01), Chen
patent: 5739709 (1998-04-01), Banno
patent: 5754080 (1998-05-01), Chen et al.
patent: 5757297 (1998-05-01), Ferraiolo et al.
patent: 5777567 (1998-07-01), Murata et al.
patent: 5778000 (1998-07-01), Dosiere et al.
patent: 5789947 (1998-08-01), Sato
patent: 5790607 (1998-08-01), Burke et al.
patent: 5799048 (1998-08-01), Farjad-Rad et al.
patent: 5808498 (1998-09-01), Donnelly et al.
patent: 5825209 (1998-10-01), Stark et al.
patent: 5834950 (1998-11-01), Co et al.
patent: 5838631 (1998-11-01), Mick
patent: 5838749 (1998-11-01), Casper et al.
patent: 5854794 (1998-12-01), Pawlowski
patent: 5910753 (1999-06-01), Bogdan
patent: 5926041 (1999-07-01), Duffy et al.
patent: 5933031 (1999-08-01), Konno
patent: 5936430 (1999-08-01), Patterson
patent: 5939901 (1999-08-01), Geddes
patent: 5950115 (1999-09-01), Momtaz et al.
patent: 5953386 (1999-09-01), Anderson
patent: 5955906 (1999-09-01), Yamaguchi
patent: 5960007 (1999-09-01), Grivna
patent: 5963058 (1999-10-01), Thomas
patent: 5963059 (1999-10-01), Partovi et al.
patent: 5969552 (1999-10-01), Lee et al.
patent: 5977801 (1999-11-01), Boerstler
patent: 6014042 (2000-01-01), Nguyen
patent: 6026134 (2000-02-01), Duffy et al.
patent: 6041090 (2000-03-01), Chen
patent: 6055286 (2000-04-01), Wu et al.
patent: 6060953 (2000-05-01), Tsai
patent: 6064235 (2000-05-01), Hayashi et al.
patent: 6075388 (2000-06-01), Dalmia
patent: 6075416 (2000-06-01), Dalmia
patent: 6081572 (2000-06-01), Filip
patent: 6088331 (2000-07-01), Beshai et al.
patent: 6100722 (2000-08-01), Dalmia
patent: 6147530 (2000-11-01), Nogawa
patent: 6194928 (2001-02-01), Heyne
patent: 6197229 (2001-03-01), Cho
patent: 6255880 (2001-07-01), Nguyen
patent: 6265996 (2001-07-01), Duffy
patent: 6307413 (2001-10-01), Dalmia et al.
patent: 6310521 (2001-10-01), Dalmia
patent: 6366135 (2002-04-01), Dalmia et al.
patent: 6404833 (2002-06-01), Takebe
patent: 6535527 (2003-03-01), Duffy
patent: 6542041 (2003-04-01), Choi
patent: 6909329 (2005-06-01), Jasa et al.
patent: 6940356 (2005-09-01), McDonald et al.
patent: 7061330 (2006-06-01), Kegasa et al.
patent: 7151413 (2006-12-01), Lin
patent: 7375593 (2008-05-01), Self
patent: 7439816 (2008-10-01), Lombaard
patent: 7443206 (2008-10-01), Fernandez
patent: 7443761 (2008-10-01), Lin
patent: 7538591 (2009-05-01), Oh
Fouzar et al., “Very Short Locking Time PLL Based on Controlled Gain Technique,” ICECS 2000—IEEE International Conference on Electronics, Circuits and Systems, Dec. 17-20, 2000, vol. 1, pp. 252-255; 4 pages.
Fouzar et al., “A New Fully Integrated CMOS Phase-Locked Loop with Low Jitter and Fast Lock Time,” ISCAS 2000—IEEE International Conference on Electronics, Circuits and Systems, May 28-31, 2000, vol. 2, pp. 253-256; 4 pages.
Wikipedia, the free encyclopedia, “Phase-Locked Loop,” <http://en.wikipedia.org/wiki/Phase-locked—loop>, May 29, 2006; 10 pages.
“1.8V, 500-MHz, 10-Output JEDEC-Compliant Zero Delay Buffer,” Cypress Advance Information, Feb. 12, 2004; 9 pages.
U.S. Appl. No. 09/301,900: “Low Latency, Low Power Deserializer,” Michael dully, Filed Apr. 29, 1999; 47 pages.
U.S. Appl. No. 08/976,072: “Circuits and Methods for Framing One or More Data Streams,” Edward Grivna, filed Nov. 21, 1997; 39 pages.
U.S. Appl. No. 08/879,287: “Phase Detector with Linear Output Response,” Navabi et al., filed Jun. 19, 1997; 14 pages.
U.S. Appl. No. 09/302,214: “Clock and Data Recovery PLL Based on Parallel Architecture,” Kamal Dalmia, filed Apr. 29, 1999; 21 pages.
U.S. Appl. No. 09/302,213: “Phase Detector with Extended Linear Range,” Kamal Dalmia, filed Apr. 29, 1999; 16 pages.
U.S. Appl. No. 09/217,465: “Phase Detector with Extended Linear Range,” Dalmia et al., filed Apr. 29, 1999; 23 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/731,606 dated Oct. 15, 2008; 11 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/731,606 dated Sep. 24, 2009; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 08/878,714 dated Jan. 6, 1999; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/731,606 dated Mar. 24, 2009; 17 pages.
USPTO Final Rejection for U.S. Appl. No. 08/878,714 dated Jun. 18, 1999; 9 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/731,606 dated Feb. 5, 2010; 6 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/541,025 dated Jun. 13, 2008; 6 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/541,025 dated Jan. 22, 2008; 6 pages.
Fouzar et al., “Very Short Locking Time PLL Based on Controlled Gain Technique,” ICECS 2000—IEEE International Conference on Electronics, Circuits and Systems, Dec. 2000, vol. 1, pp. 252-255; 4 pages.
Fouzer et al., “A New Fully Integrated CMOS Phase-loocked Loop with Low Jitter and Fast Lock Time,” ISCAS 2000—IEEE International Conference on Electronics, Circuits and Systems, May 2000, vol. 2, pp. 253-256; 4 pages.
“Phase-Locked Loop,” <http://en.wikipedia.org/wiki/Phase-locked—loop>, May 29, 2006; 10 pages.
“1.8V, 500MHz, 10-Output JEDEC-Compliant Zero Delay Buffer,” Cypress Advanced Information, Feb. 12, 2004; 9 pages.
USPTO Notice of Allowance for U.S. Appl. No. 08/878,714 dated Sep. 27, 1999; 6 pages.
USPTO Restriction Requirement for U.S. Appl. No. 09/301,900 dated Aug. 23, 2000; 2 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/818,740 dated Feb. 19, 2010; 7 pages.
USPTO Notice of Allowance for U.S. Appl. N
Cypress Semiconductor Corporation
Odom Curtis B
LandOfFree
Symmetrical range controller circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Symmetrical range controller circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Symmetrical range controller circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2664885