Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-02-22
2001-06-12
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220, C365S185280
Reexamination Certificate
active
06246610
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to methods to program and erase a memory cell.
RELATED ART
FIG. 1
illustrates a cross sectional view of a conventional memory transistor, also known as a memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2
schematically illustrates a conventional NAND type flash memory array
100
that includes numerous memory cells, each depicted in
FIG. 1. A
“string” includes a selection transistor T
i−1
, memory transistors M
i−1
to M
i−j
, and a selection transistor T
i−2
, all being serially coupled. Each string can be coupled to a bit line BLj and a common source CS through selection transistors T
i 1
, and T
i−2
, respectively. The control gates for selection transistors T
i−1
and T
i−2
are respectively connected to selection lines Sl
1
and Sl
2
. The control gates for the memory transistors M
i−1
, to M
i−j
are respectively connected to word lines W
1
to W
j
. Typically, a read operation is performed on a page basis, i.e., flash memory cells coupled to a word line are read together.
Herein, a memory transistor represents logical LOW when it is programmed to have a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits. Correspondingly, a memory transistor represents a logical HIGH when it is erased to have a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits. One skilled in the art will understand that logic level assignments to the predetermined minimum and maximum threshold voltages are arbitrary.
A large variation in the programming and erasing characteristics of individual NAND type flash memory transistors among a memory array is common. The variations can be due to structural differences, which cause difference in threshold voltage characteristics. Such variations introduce differences in programming and erasing speeds among memory transistors. Conventional NAND type flash memory arrays use fixed programming and erase voltages that cannot adjust to programming and erasing characteristics of the memory transistors. Some memory transistors in flash memory arrays do not respond to the fixed programming and erase voltages of NAND type flash memory arrays. Accordingly, NAND type flash memory arrays that include an intolerably high number of non-responsive memory cells are typically discarded. As such, the yield of usable NAND memory arrays fluctuates. Low yield increases the manufacturing cost of NAND memory, and hence leads to a less profitable and less competitive position.
Thus what is needed is a method and apparatus to adaptively control the programming and erase voltages of NAND type flash memory and thereby increase the proportion of usable memory cells.
SUMMARY
In one embodiment of the present invention, a method for programming and erasing a nonvolatile memory device comprises applying a program voltage and applying an erase voltage, where the program voltage is approximately equal to the erase voltage.
In another embodiment of the present invention, a method for programming and erasing a nonvolatile memory device comprises applying a set of program voltages and applying an erase voltage, where the average voltage of the set of program voltages is approximately equal to the erase voltage.
In another embodiment of the present invention, a method for selecting program voltages and an erase voltage for a nonvolatile memory device comprises determining a set of program voltages that programs the nonvolatile memory device within a first specified time, determining an erase voltage that erases the nonvolatile memory device within a second specified time, and determining if the average voltage of the set of program voltages is approximately equal to the erase voltage.
It is believed that the above methods provide a symmetry in the program and erase voltages that slows erase time degradation, thereby extending the usable program/erase cycles of nonvolatile memory devices.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
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Chang Chi
Derhacobian Narbeh
Han K. Michael
Pawletko Joseph G.
Advanced Micro Devices , Inc.
Hsia David C.
Kwok Edward C.
Mai Son
Skjerven Morrill & MacPherson LLP
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