Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1997-12-22
2001-08-14
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06275064
ABSTRACT:
BACKGROUND
1. Field of the Invention
The invention is generally directed to integrated circuits, more specifically to Programmable Logic Devices (PLDs), and even more specifically to a subclass of PLDs known as Field Programmable Gate Arrays (FPGAs).
(A) Ser. No. 08/828,520, now U.S. Pat. No. 5,905,385, filed Apr. 1, 1997 by Bradley A. Sharpe-Geisler and originally entitled, “MEMORY BITS USED TO COUPLE LOOK UP TABLE INPUTS TO FACILITATE INCREASED AVAILABILITY TO ROUTING RESOURCES PARTICULARLY FOR VARIABLE SIZED LOOK UP TABLES FOR A FIELD PROGRAMMABLE GATE ARRAY (FPGA)”;
(B) Ser. No. 08/931,798, filed Sep. 16, 1997 by Bradley A. Sharpe-Geisler and originally entitled, “CIRCUITRY TO PROVIDE FAST CARRY”;
(C) Ser. No. 08/700,616, now U.S. Pat. No. 5,740,069 filed Aug. 16, 1996 by Om Agrawal et al. and entitled, “PROGRAMMABLE LOGIC DEVICE (PLD) HAVING DIRECT CONNECTIONS BETWEEN CONFIGURABLE LOGIC BLOCKS (CLBs) AND CONFIGURABLE INPUT/OUTPUT BLOCKS (IOBs) (AS AMENDED)” (as a continuing divisional with chained cross referencing back to Ser. No. 07/394,221 filed Aug. 15, 1989);
(D) Ser. No. 08/912,763 filed Aug. 18, 1997, by Bradley A. Sharpe-Geisler and originally entitled, “OUTPUT BUFFER FOR MAKING A 2.5 VOLT CIRCUIT COMPATIBLE WITH A 5.0 VOLT CIRCUIT”;
(E) Ser. No. 08/948,306 filed Oct. 9, 1997, by Om Agrawal et al. and originally entitled, “VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS”;
(F) Ser. No. 08/966,049 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “DUAL PORT SRAM MEMORY FOR RUN-TIME USE IN FPGA INTEGRATED CIRCUITS”;
(G) Ser. No. 08/995,615 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “A PROGRAMMABLE INPUT/OUTPUT BLOCK (IOB) IN FPGA INTEGRATED CIRCUITS”;
(H) Ser. No. 08/995,614, now U.S. Pat. No. 5,982,193, filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “INPUT/OUTPUT BLOCK (IOB) CONNECTIONS TO MAXL LINES, NOR LINES AND DENDRITES IN FPGA INTEGRATED CIRCUITS”;
(I) Ser. No. 08/995,612, now U.S. Pat. No. 5,990,702, filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “FLEXIBLE DIRECT CONNECTIONS BETWEEN INPUT/OUTPUT BLOCKs (IOBs) AND VARIABLE GRAIN BLOCKs (VGBs) IN FPGA INTEGRATED CIRCUITS”;
(J) Ser. No. 08/997,221 filed Dec. 22, 1997, by Om Agrawal et al. and originally entitled, “PROGRAMMABLE CONTROL MULTIPLEXING FOR INPUT/OUTPUT BLOCKs (IOBs) IN FPGA INTEGRATED CIRCUITS”;
(K) Ser. No. Not Yet Known filed Dec. 22, 1997, by Bradley Sharpe-Geisler and originally entitled, “MULTIPLE INPUT ZERO POWER AND/NOR GATE FOR USE WITH A FIELD PROGRAMMABLE GATE ARRAY (FPGA)”; and,
(L) Ser. No. 08/996,492 filed Dec. 22, 1997, by Bradley Sharpe-Geisler and originally entitled, “INPUT BUFFER PROVIDING VIRTUAL HYSTERESIS”.
2. Description of Related Art
Field-Programmable Logic Devices (FPLDs) have continuously evolved to better serve the unique needs of different end-users. From the time of introduction of simple PLDs such as the Advanced Micro Devices 22V10 Programmable Array Logic device (PAL), the art has branched out in several different directions.
One evolutionary branch of FPLDs has grown along a paradigm known as Complex PLDs or CPLDs. This paradigm is characterized by devices such as the Advanced Micro Devices MACH family. Examples of CPLD circuitry are seen in U.S. Pat. No. 5,015,884 (issued May 14, 1991 to Om P. Agrawal et al.) and U.S. Pat. No. 5,151,623 (issued Sep. 29, 1992 to Om P. Agrawal et al.).
Another evolutionary chain in the art of field programmable logic has branched out along a paradigm known as Field Programmable Gate Arrays or FPGAs. Examples of such devices include the XC2000 and XC3000 families of FPGA devices introduced by Xilinx, Inc. of San Jose, Calif. The architectures of these devices are exemplified in U.S. Pat. Nos. 4,642,487; 4,706,216; 4,713,557; and 4,758,985; each of which is originally assigned to Xilinx, Inc.
An FPGA device can be characterized as an integrated circuit that has four major features as follows.
(1) A user-accessible, configuration-defining memory means, such as SRAM, EPROM, EEPROM, anti-fused, fused, or other, is provided in the FPGA device so as to be at least once-programmable by device users for defining user-provided configuration instructions. Static Random Access Memory or SRAM is of course, a form of reprogrammable memory that can be differently programmed many times. Electrically Erasable and reprogrammable ROM or EEPROM is an example of nonvolatile reprogrammable memory. The configuration-defining memory of an FPGA device can be formed of mixture of different kinds of memory elements if desired (e.g., SRAM and EEPROM).
(2) Input/Output Blocks (IOBs) are provided for interconnecting other internal circuit components of the FPGA device with external circuitry. The IOBs' may have fixed configurations or they may be configurable in accordance with user-provided configuration instructions stored in the configuration-defining memory means.
(3) Configurable Logic Blocks (CLBs) are provided for carrying out user-programmed logic functions as defined by user-provided configuration instructions stored in the configuration-defining memory means. Typically, each of the many CLBs of an FPGA has at least one lookup table (LUT) that is user-configurable to define any desired truth table, —to the extent allowed by the address space of the LUT. Each CLB may have other resources such as LUT input signal pre-processing resources and LUT output signal post-processing resources. Although the term ‘CLB’ was adopted by early pioneers of FPGA technology, it is not uncommon to see other names being given to the repeated portion of the FPGA that carries out user-programmed logic functions. The term, ‘LAB’ is used for example in U.S. Pat. No. 5,260,611 to refer to a repeated unit having a
4
-input LUT.
(4) An interconnect network is provided for carrying signal traffic within the FPGA device between various CLBs and/or between various IOBs and/or between various IOBs and CLBS. At least part of the interconnect network is typically configurable so as to allow for programmably-defined routing of signals between various CLBs and/or IOBs in accordance with user-defined routing instructions stored in the configuration-defining memory means. Another part of the interconnect network may be hard wired or nonconfigurable such that it does not allow for programmed definition of the path to be taken by respective signals traveling along such hard wired interconnect. A version of hard wired interconnect wherein a given conductor is dedicatedly connected to be always driven by a particular output driver, is sometimes referred to as ‘direct connect’.
Modern FPGAs tend to be fairly complex. They typically offer a large spectrum of user-configurable options with respect to how each of many CLBs should be configured, how each of many interconnect resources should be configured, and how each of many IOBs should be configured. Rather than determining with pencil and paper how each of the configurable resources of an FPGA device should be programmed, it is common practice to employ a computer and appropriate FPGA-configuring software to automatically generate the configuration instruction signals that will be supplied to, and that will cause an unprogrammed FPGA to implement a specific design.
FPGA-configuring software typically cycles through a series of phases, referred to commonly as ‘partitioning’, ‘placement’, and ‘routing’. This software is sometimes referred to as a ‘place and route’ program. Alternate names may include, ‘synthesis, mapping and optimization tools’.
In the partitioning phase, an original circuit design (which is usually relatively large and complex) is divided into smaller chunks, where each chunk is made sufficiently small to be implemented by a single CLB, the single CLB being a yet-unspecified one of the many CLBs that are available in the yet-unprogrammed FPGA device. Differently designed FPGAs can have differently designed CLBs with respective logic-implementing resources. As such, the maximum size of a partitioned chunk can vary in accordance with the
Agrawal Om P.
Chang Herman M.
Sharpe-Geisler Bradley A.
Tran Giap H.
Fliesler Dubb Meyer & Lovejoy LLP
Vantis Corporation
Wamsley Patrick
LandOfFree
Symmetrical, extended and fast direct connections between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Symmetrical, extended and fast direct connections between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Symmetrical, extended and fast direct connections between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2464129