Symmetric multiprocessing system with unified environment...

Details Symmetric multiprocessing system with unified environment... Symmetric multiprocessing system with unified environment...

1994-06-10

2001-10-30

Banankhah, Majid (Department: 2151)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C365S230030, C365S063000, C365S052000

Reexamination Certificate

active

06311286

ABSTRACT:

1 . Field of the Invention
The present invention relates to an improved data processing system and, in particular, to a symmetric data processing system with unified process environment and distributed system functions.
2. Discussion of the Prior Art
A recurring problem in symmetric multiprocessing systems of the prior art, that is, in systems having a plurality of processes wherein any of a plurality of multi-threaded processes may be executed concurrently or in any sequence on any of a plurality of processors, is in providing an environment which is unified from the viewpoint of the processes executing therein but wherein the system functions, such as memory space management, bus access, and data management, are not concentrated in a single processor. Such concentration of system functions, usually resulting from an attempt to present a unified processing environment, presents fundamental limitations in the capabilities of the centralized facility for performing such functions have an upper limit. The use of centralized system functions frequently results in a non-unified environment in that a centralized system cannot handle or even be aware of the requirements of each functional unit in the system.
SUMMARY OF THE INVENTION
The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a block diagram of a system incorporating the present invention;
FIG. 2
is a block diagram of a memory controller;
FIG. 3
is a block diagram of a memory data path;
FIG. 4
is a block diagram of a correction queue;
FIG. 5
is a block diagram of adaptive memory timing logic;
FIG. 6
is a block diagram of an in-order request/response queue;
FIG. 7
is a block diagram of address space mapping;
FIG. 8
is a block diagram of a bus access arbitration mechanism;
FIG. 9
is a block diagram of an I/O bridge;
FIG. 10
is a block diagram of a bridge bus interface controller;
FIG. 11
is a block diagram of a bridge cache;
FIG. 12
is a block diagram of a bridge interface controller for a write request;
FIG. 13
is a block diagram of a bridge controller for a read request;
FIG. 14
is a block diagram of a bridge controller for a bus window;
FIG. 15
is a block diagram of a bridge interface register data path;
FIG. 16
is a block diagram of a bridge interface controller and snoop;
FIG. 17
is a flow chart of snooping on a write request;
FIG. 18
is a flow chart of snooping on a read request;
FIG. 19
is a block diagram of a personal computer;
FIG. 20
is a block diagram of a processor functional unit;
FIG. 21
is a block diagram of a memory bus controller;
FIG. 22
is a block diagram of a memory bus controller control structure; and,
FIG. 23
is a block diagram of a processor data path.


REFERENCES:
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5253358 (1993-10-01), Thoma, III et al.
patent: 5272664 (1993-12-01), Alexander et al.
patent: 5293603 (1994-03-01), MacWilliams et al.
patent: 5355467 (1994-10-01), MacWilliams et al.
patent: 5418924 (1995-05-01), Dresser
Popcat, High-Performance PC/AT-Compatible chip set date Manual, Logic product Division, Nov. 1989.

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