Image analysis – Image compression or coding – Pyramid – hierarchy – or tree structure
Reexamination Certificate
1999-02-24
2001-04-10
Au, Amelia (Department: 2623)
Image analysis
Image compression or coding
Pyramid, hierarchy, or tree structure
C375S240190, C382S263000, C382S264000
Reexamination Certificate
active
06215908
ABSTRACT:
BACKGROUND
(1) Field
The present invention relates to signal/image processing. More specifically, the present invention relates to image compression.
(2) Background Information
Using traditional Fourier analysis transforms, any signal may be approximated as a sum of sinusoidal waveforms of assorted frequencies. While Fourier transforms are ideally suited for signals having repeated behavior, such as speech signals, Fourier transforms fail to efficiently approximate signals with sharp discontinuities such as the edge features of images, or signals encoded for digital communications.
Wavelets are used as a way to represent an image in both the frequency and spatial domain. Due to quantization effects, less visual side effects are produced when using wavelets compared to a block based discrete cosine transform (DCT). A transform, similar to the Fourier transform, Discrete Wavelet Transform (DWT), based on Wavelet analysis, has been developed to represent signals with discontinuous features. The DWT is a “discrete” algorithm, that rather than approximating a signal using continuous waveforms, approximates the signal by discrete samples of waveforms. Since the transform is discrete, the DWT may be implemented using digital logics such as Very Large Scale Integrated (VLSI) circuits. Thus DWT may be integrated on a chip with other digital components.
The essence of DWT is to decompose an input signal into two or more frequency sub-bands. An input signal may be decomposed into two outputs—a low frequency sub-band output, obtained by using a low-pass filter, and a high frequency sub-band output, obtained by using a high-pass filter. Each of these sub-bands may be encoded separately using a suitable coding system. Each sub-band may further be divided into smaller and smaller sub-bands as is required.
In general, DWT is a computationally very intensive process and hence very slow when computed using a general purpose computing system. To make it suitable for real-time applications, a special purpose custom VLSI chip may be used for DWT, exploiting the underlying data parallels to yield high throughput and hence high data rate. Several VLSI architectures for DWT have been proposed. However, most of these complex architectures require large hardware area and yield much less than 100 percent hardware utilization. It is desirable to provide a new DWT architecture for performing image compression that utilizes a reduced number of hardware parts.
SUMMARY
Briefly, in one embodiment, the present invention provides an apparatus to perform symmetric filtering image compression. The apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image. The apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs. The apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs. Additionally, the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits. The apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits.
REFERENCES:
patent: 4829585 (1989-05-01), Pape
patent: 4943855 (1990-07-01), Bheda et al.
patent: 5706220 (1998-01-01), Vafai et al.
patent: 5889559 (1999-03-01), Yang
patent: 5999656 (1999-12-01), Zandi et al.
Kim, Image compression using biorthogonal wavelet transforms with multiplierless 2-D filter mask operation, 10/1997, pp. 648-651, IEEE Image Processing.*
A High Speed Reconfigurable Intergrated Architecture for DWT, Global Tlecommunications Conference, New York, IEEE, Nov. 9, 1997, pp. 669-673 Achayra.
Fast and Low roundoff Implementation of Quadrature Mirror Filters for Subband Coding, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Inc., New York, vol. 5, No. 6, Dec. 1, 1995, pp. 524-532 Yang et al.
A VLSI Architecture for Separable 2-D Discrete Wavelet Transform, Journal of VLSI Signal Processing, NL, Kluwer Academic Publishers, vol. 18, No. 2, Feb. 1, 1998, pp. 125-139 Limqueco et al.
Acharya Tinku
Pazmino Edward A.
Vavro David K.
Au Amelia
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Johnson Timothy M.
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