Symmetric current mode logic

Details Symmetric current mode logic Symmetric current mode logic

2002-10-09

2004-03-02

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

C326S091000, C326S052000

Reexamination Certificate

active

06700413

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a symmetric current mode logic and, more particularly, to a current mode logic with symmetric input loads at the input terminals so as to overcome the limitations due to the difference between the input loads or the level demands and to further avoid signal surges due to current steering.
2. Description of the Prior Art
In a conventional current mode logic, because of the difference between the input loads or the level demands, serious signal surges due to current steering may take place at the output terminals when the logic is in operation, resulting in malfunction of the whole circuit. The logic levels at the two input terminals of a conventional current mode logic are different for a certain number of logic functions and the input loads seen at the input terminals are also different. Therefore, considerable limitations on applications are inevitable.
Please refer to
FIG. 1
, which is a schematic circuit diagram showing conventional current mode XOR (exclusive OR) logic. Ah shown in
FIG. 1
, the logic circuit comprises two differential amplifiers, in which a first differential amplifier includes a first input terminal A and a second input terminal AB and a second differential amplifier includes a third input terminal B and a fourth input terminal BB. When the third input terminal B is at a logical “1” and the fourth input terminal BB is at a logical “0”, a first transistor Q
1
is ON and a fourth transistor Q
4
is OFF. Meanwhile, a first output terminal OUT is determined by a third transistor Q
3
and a second output terminal OUTB is determined by a fourth transistor Q
4
. On the contrary, when the third input terminal B is at a logical “0” and the fourth input terminal BB is at a logical “1”, the first transistor Q
1
is OFF and the fourth transistor Q
4
is ON. Meanwhile, the first output terminal OUT is determined by a sixth transistor Q
6
and the second output terminal OUTB is determined by a fifth transistor Q
5
. Therefore, the first output terminal OUT outputs the result after an XOR operation of the first input terminal A and the third input terminal B, while the second output terminal OUTB outputs the result after an XNOR operation of the first input terminal A and the third input terminal B.
In the aforementioned logic circuit, the logical level at the first input terminal A is based on the third input terminal B. In other words, the logical level required for the first input terminal A is different from the logical level required for the third input terminal B. Therefore, two current steering cases may occur in such a dual-level current mode logic, in which an alternation of the first transistor Q
1
and the fourth transistor Q
4
follows the alternation of the second transistor Q
2
and the third transistor Q
3
or the alternation of the fifth transistor Q
5
and the sixth transistor Q
6
. Meanwhile, current steering resulting from the alternation of these transistors leads to serious signal surges at the output terminals. During the operation of the logic circuit, serious signal surges may take place due to stack CML current steering when the two transistors are ON simultaneously. For example, when the logic level at the first input terminal A and the logic level at the third input terminal B are both turned into a logical “1” from a logical “0”, the XOR of the first input terminal A and the third input terminal B (A XOR B) should remain as a logical “0”, i.e., OUT=(A·BB)+(AB·B). In short, both the first output terminal OUT and the second output terminal OUTB are kept as a logical “0”. However, signal surges may happen because of current steering.
Even though current steering is inevitable when the current mode logic is in operation, serious signal surges may, however, be avoided by using a single-level logic circuit configuration instead of a dual-level logic circuit configuration so as to prevent stack current steering. In the prior art, the input load seen at the first input terminal A and the input load seen at the third input terminal B of the current mode logic are different. Moreover, the logic level at the second input terminal AB and the logic level at the fourth input terminal BB are different such that both of the first transistor Q
1
and the fourth transistor Q
4
operate in an active region. All these limit the applications of the conventional XOR logic circuits.
Therefore, there is need for providing a symmetric current mode logic employing a single-level logic with parallel switching so as to overcome serious signal surges resulting from stack current steering. Furthermore, the logic levels and the input loads at respective input terminals are identical by virtue of the single-level logic.
SUMMARY OF THE INVENTION
It is the primary object of the present invention to provide a symmetric current mode logic with symmetric input loads as well as identical input logic levels at the input terminals so as to prevent phase error due to level adjustment and to further avoid signal surges due to current steering by parallel switching.
In order to achieve the foregoing object, the present invention provides a symmetric current mode logic, comprising: an output circuit comprising a plurality of input terminals and two differential amplifiers sharing a pair of output terminals being a first output terminal and a second output terminal; and a plurality of input circuits functioning as a plurality of symmetric current mode logic units, each comprising a plurality of signal output terminals connected to said plurality of input terminals of said output circuit so as to form a single-level logic circuit.


REFERENCES:
patent: 5355035 (1994-10-01), Vora et al.
patent: 2002/0084806 (2002-07-01), Yang

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