Symmetric blocking transient voltage suppressor (TVS) using...

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Reexamination Certificate

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C365S072000, C365S189060, C327S310000

Reexamination Certificate

active

07554839

ABSTRACT:
A symmetrical blocking transient voltage suppressing (TVS) circuit for suppressing a transient voltage includes an NPN transistor having a base electrically connected to a common source of two transistors whereby the base is tied to a terminal of a low potential in either a positive or a negative voltage transient. The two transistors are two substantially identical transistors for carrying out a substantially symmetrical bi-directional clamping a transient voltage. These two transistors further include a first and second MOSFET transistors having an electrically interconnected source. The first MOSFET transistor further includes a drain connected to a high potential terminal and a gate connected to the terminal of a low potential and the second MOSFET transistor further includes a drain connected to the terminal of a low potential terminal and a gate connected to the high potential terminal.

REFERENCES:
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patent: 5495118 (1996-02-01), Kinoshita et al.
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patent: 6046897 (2000-04-01), Smith et al.
patent: 6770918 (2004-08-01), Russ et al.
patent: 6882576 (2005-04-01), Tomita
patent: 7030447 (2006-04-01), Robb et al.
patent: 2006/0066408 (2006-03-01), Fang et al.
patent: 2007/0279824 (2007-12-01), Mallikararjunaswamy

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