Television – Synchronization – Automatic phase or frequency control
Patent
1997-05-07
1999-01-12
Grant, Chris
Television
Synchronization
Automatic phase or frequency control
348500, 375355, H04N 512
Patent
active
058596712
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a digital television receiver, and more particularly to a circuit and method for recovering a symbol timing in order to accurately demodulate transmission signals.
BACKGROUND ART
Digital receivers should use a demodulator synchronized with the symbol transition of an input digital signal for optimal demodulation. Since the receiver including a channel equalizer is usually operated by a digital circuit, a received analog signal can be converted to a digital signal through an analog-to-digital converter at an accurate sampling time. That is, since a signal processing operation is carried out after the analog signal is converted to the digital signal, the digital receiver can implement a normal operation when data is accurately generated at the sampling time.
In digital high picture quality television systems, the GA (Grand Alliance) system uses, as a carrier wave, a pilot signal having a direct current (DC) value of about 1.25 during data transmission so as to easily recover the carrier wave at a receiving end. Therefore, data received from the receiver includes the DC component by the pilot signal. If a timing error component is directly detected from the received data, it is difficult to detect a correct timing error value by the influence of the DC component.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide a symbol timing recovery circuit and method for demodulating a transmission signal without an error by detecting a phase error in a received data segment synchronizing signal and compensating for the detected phase error.
A symbol timing recovery circuit of a digital television embodying the present invention includes: an analog-to-digital converter for sampling a received analog signal by a symbol clock to be converted to digital data; demodulator for recovering a carrier wave, demodulating the digital data to a baseband signal and generating a segment signal; a segment synchronizing signal detector for detecting a segment synchronizing signal from the segment signal; a phase error detector activated by the segment synchronizing signal, for receiving the segment signal and detecting a phase error of synchronizing symbols of the segment synchronizing signal; and a symbol clock phase adjuster for adjusting the phase of the symbol clock according to the phase error of the synchronizing symbols to be supplied to the analog-to-digital converter as the symbol clock.
BRIEF DESCRIPTION OF DRAWINGS
For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals designate like or corresponding parts throughout the several views, and in which:
FIG. 1 is a block diagram of a symbol timing recovery circuit according to the present invention;
FIGS. 2A, 2B and 2C show variations in a segment synchronizing signal according to a symbol timing error;
FIG. 3 is a more detailed block diagram of the symbol timing recovery circuit of FIG. 1;
FIG. 4 is a more detailed block diagram of a segment synchronizing signal detector shown in FIGS. 1 and 3; and
FIG. 5 is another more detailed block diagram of the symbol timing recovery circuit of FIG. 1.
BEST MODE FOR CARRYING OUT THE INVENTION
In the following description, a "digital high picture quality television" indicates a high resolution television of the GA (Grand Alliance) system. A "segment signal" or a "data segment signal" is a signal of 832 symbols including data of 828 symbols and a synchronizing signal of 4 symbols and means a signal of one horizontal line. A "synchronizing signal" or a "segment synchronizing signal" represents 4 (first to fourth) synchronizing symbols for notifying the beginning of the data segment signal. The first and fourth synchronizing symbols have a signal level of +5, and the second and third synchronizing symbols have a signal level of -5.
FIG. 1 shows a symbol timing recovery circuit of a digital hi
REFERENCES:
patent: 4805191 (1989-02-01), Burch et al.
patent: 4815103 (1989-03-01), Cupo et al.
patent: 5285482 (1994-02-01), Seheir et al.
patent: 5369668 (1994-11-01), Yamamoto
patent: 5388127 (1995-02-01), Scarpa
patent: 5565932 (1996-10-01), Citta et al.
patent: 5572249 (1996-11-01), Ghoxh
patent: 5594506 (1997-01-01), Yang
Grant Chris
Samsung Electronics Co,. Ltd.
LandOfFree
Symbol timing recovery circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Symbol timing recovery circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Symbol timing recovery circuit and method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1520878