Symbol timing recovery based on adjusted, phase-selected magnitu

Details Symbol timing recovery based on adjusted, phase-selected magnitu Symbol timing recovery based on adjusted, phase-selected magnitu

1999-05-03

2000-11-28

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375326, 327141, 327147, H04L 700

Patent

active

061545104

ABSTRACT:
A digital communication receiver (10) includes a magnitude-based symbol synchronizer (38) which separates complex phase attributes from magnitude attributes. The phase attributes are processed by a phase processor (78) which identifies clock adjustment opportunities. The magnitude attributes are processed by a magnitude processor (76) that generates a phase error estimate signal (82), which in turn drives a clock generator (24) in a phase locked loop (54) to achieve symbol synchronization in a non-data-directed manner. An additional adjustment feedback loop (114, 128) includes a phase error offset generator (52) and operates in conjunction with the phase locked loop (54) to allow the phase locked loop (54) to achieve lock and a robust operating point in spite of distortion in a received input analog signal (12).

REFERENCES:
patent: 4215239 (1980-07-01), Gordy et al.
patent: 5440265 (1995-08-01), Cochran et al.
patent: 5671257 (1997-09-01), Cochran et al.
patent: 5764102 (1998-06-01), Cochran et al.
patent: 5862191 (1999-01-01), Moridi
Lars Erup, et al., "Interpolation in Digital Modems-Part II: Implementation and Performance", IEEE Transactions on Communications, vol.-41, No. 6, Jun. 1993, pp 998-1007.
K. Bucket et al., "Symbol Synchronizer Performance Affected by Non-Ideal Interpolation in Digital Modems" 1994, IEEE, pp 929-933.

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