Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-08-15
2006-08-15
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07093183
ABSTRACT:
Error correction and detection codes are designed with several properties: the ability to perform error correction and detection operations via syndrome generation in multiple cycles of information delivery from a source such as a set of memory chips; a code structure which is cooperatively designed in terms of the bits-per-chip architecture of a set of memory chips so as to provide enhanced robustness in the face of bus line and chip failures; and a structured parity check matrix which provides circuits which are cheaper, take up less room, and are faster than standard designs.
REFERENCES:
patent: 4525838 (1985-06-01), Patel
patent: 5600659 (1997-02-01), Chen
Gui-Liang Feng et al. ‘A new procedure for decoding cyclic and BCH codes up to actual minimum distance,’IEEE Transaction on Information Theory, Sep. 1994, pp. 1364-1374, vol. 40, Issue: 5.
Cutter Lawrence D.
Kinnaman, Jr. William A.
Lamarre Guy J.
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