SWL ferroelectric memory and circuit for driving the same

Static information storage and retrieval – Systems using particular element – Ferroelectric

Patent

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Details

365149, 36523006, G11C 1122

Patent

active

060916249

ABSTRACT:
A split wordline ferroelectric memory does not utilize plate lines and a circuit for driving the same is disclosed. The memory including unit cell arrays and each array has a plurality of split wordlines (SWLs) arranged in a first direction at fixed intervals, and a plurality of bitlines arranged in a second direction vertical to each of the SWLs at fixed intervals. A ferroelectric unit memory cell is arranged in each pair of adjacent two SWLs and adjacent two bitlines. The circuit includes a post X-decoder for receiving and decoding X and Z-addresses for controlling a cell array block operative, a global control pulse generator for providing a control pulse required for data write or read in response to a CSBpad signal received externally, a local control pulse generator for receiving the control pulse from the global control pulse generator and providing a control signal required for data write and read, an SWL cell array block for storage of data, an SWL driver for driving the SWL cell array block in response to control signals from the post X-decoder and the local control pulse generator, a Y-address decoder for decoding a Y-address signal received externally, a column controller for controlling columns in response to the control signal from the local control pulse generator and a decoded signal from the Y-address decoder, and a sense amplifier and I/O controller for sensing/recording a data from/to the SWL cell array block.

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