Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
1999-11-09
2001-10-23
Pham, Chi (Department: 2631)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C370S516000
Reexamination Certificate
active
06307905
ABSTRACT:
The present invention is related to the following co-pending applications filed on the same day as the present invention and assigned to the same assignee, the contents of each of which are herein incorporated by reference: Ser. No. 09/437,721 entitled “Timing Recovery System for a Multi-Pair Gigabit Transceiver” and Ser. No. 09/437719 entitled “Multi-Pair Gigabit Ethernet Transceiver”.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to switching noise and clock signals in a transceiver. More particularly, the present invention relates to a method and a system for generating and distributing clock signals in a gigabit Ethernet transceiver, which includes more than one constituent transceiver, such that effect of switching noise is minimized.
2. Description of Related Art
A transceiver includes a transmitter and a receiver. In a traditional half-duplex transceiver, the transmitter and the receiver can operate with a common clock signal since the transmitting and receiving operations do not occur simultaneously.
In a full-duplex transceiver, the transmitting operation occurs simultaneously with the receiving operation. The full-duplex transceiver needs to operate with at least two clock signals, a transmit clock signal (TCLK) and a sampling clock signal. The TCLK signal is used by the transmitter to regulate transmission of data symbols. The sampling clock signal is used by the receiver to regulate sampling of the received signal at an analog-to digital (A/D) converter. At the local receiver, the frequency and phase of the sampling clock signal are adjusted by a timing recovery system of the local receiver in such a way that they track the transmit clock signal of the remote transmitter. The sampled received signal is demodulated by digital signal processing function blocks of the receiver. These digital processing functions blocks may operate in accordance with either the TCLK signal or the sampling clock signal, provided that signals crossing boundaries between the two clock signals are treated appropriately so that any loss of signal or data samples is prevented.
The IEEE 802.3ab standard (also called 1000BASE-T) for 1 gigabit per second (Gb/s) Ethernet full-duplex communication system specifies that there are four constituent transceivers in a gigabit transceiver and that the full-duplex communication is over four twisted pairs of Category-5 copper cables. Since a Gigabit Ethernet transceiver has four constituent transmitters and four constituent receivers, its operation is much more complex than the operation of a traditional full-duplex transceiver. The four twisted pairs of cable may introduce different delays on the signals, causing the signals to have different phases. This, in turn, requires the gigabit Ethernet transceiver to have four A/D converters operating in accordance with four respective sampling clock signals. In addition, the problem of switching noise coupled from the digital signal processing blocks of the gigabit Ethernet transceiver to the four A/D converters must also be addressed.
Therefore, there is a need to have an efficient method and system for generating the clock signals for a gigabit Ethernet transceiver. There is also a need to distribute the clock signals such that effect of switching noise is minimized.
SUMMARY OF THE INVENTION
The present invention provides a method and a system for reducing system performance degradation caused by switching noise in a system which includes a set of subsystems. Each of the subsystems includes an analog section and a digital section. Each of the analog sections operates in accordance with a corresponding one of a set of sampling clock signals which are synchronous in frequency. The digital sections operate in accordance with a receive clock signal. The receive clock signal is generated such that it is synchronous in frequency with the sampling clock signals and has a phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
REFERENCES:
patent: 5825777 (1998-10-01), Komarek et al.
IEEE Std 802.3ab-1999 (Supplement to IEEE Std 802.3, 1998 Edition), entitled Supplement to Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications—Physical Layer Parameters and Specifications for 1000 Mb/s Operation Over 4-Pair of Category 5 Balanced Copper Cabling, Type 1000BASE-T.
Broadcom Corporation
Christie Parker & Hale LLP
Corrielus Jean B.
Pham Chi
LandOfFree
Switching noise reduction in a multi-clock domain transceiver does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Switching noise reduction in a multi-clock domain transceiver, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switching noise reduction in a multi-clock domain transceiver will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2602672