Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-02-24
2002-04-30
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C710S120000, C714S006130, C714S006130
Reexamination Certificate
active
06381675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a disk array apparatus and in particular, to a disk array apparatus including a disk apparatus of specification allowing only a single initiator. The present invention also relates to a switch circuit for selectively connecting such a disk apparatus to a disk controller.
2. Description of the Related Art
Conventionally, a disk array system using a plurality of magnetic disks has been used so as to increase the data transfer speed and to enable to restore a data even if a trouble has occurred. In a conventional disk array apparatus, the interface of the magnetic disk apparatuses is usually of SCSI specification. In a magnetic disk apparatus of SCSI specification can recognize a plurality of initiators through the arbitration function. Accordingly, in order to assure a reliability of the entire disk array apparatus, a plurality of array controllers are connected. In this case, each of the magnetic disk apparatuses can recognize the respective array controllers.
However, in case of the SCSI specification, the apparatus itself has various functions and the magnetic disk apparatus becomes complicated, which in turn makes the entire disk array system complicated. Furthermore, a magnetic disk of SCSI specification can recognize a plurality of initiators. This requires a selection processing between the initiator and a target. This selection processing lowers the bus efficiency and the entire data transfer speed.
Moreover, the SCSI specification is based on a general-purpose design concept and the apparatus itself has various functions, resulting in a high price. Furthermore, as shown in
FIG. 10
, if a data transfer is increased by independent bus control without sharing a bus, SCSI controllers
55
a
to
55
j
for the magnetic disk apparatuses should be mounted on a control package
50
a
and
50
b.
This also results in increasing the cost of entire disk array apparatus.
On the other hand, in case of a magnetic disk apparatus of the ATA specification in which the magnetic disk apparatus itself is not expensive, the magnetic disk apparatus itself allows only a single initiator and it is impossible to use a plurality of array controllers as the initiator. Accordingly, it is impossible to assure a sufficient reliability of the disk array apparatus as a whole.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a disk array apparatus enabling a high data transfer rate at a reasonable cost with a high reliability as well as a switch circuit used for the disk array apparatus.
The present invention provides a disk array apparatus that can enhance the aforementioned reliability even if a disk apparatus allows only a single initiator, and a switch circuit used for the disk array apparatus.
The switching mechanism according to the present invention comprises: a plurality of array controller connectors connected to a first signal line for a data transfer to/from a plurality of array controllers; a plurality of disk apparatus connectors connected to a second signal line for a data transfer to/from a disk apparatus in which writing/reading of the data is controlled by the array controllers; and a plurality of connection lines for connections between the plurality of array controller connectors and the disk apparatus connectors; a plurality of switch circuits provided on the connection lines for one-to-one connection between the plurality of array controller connectors and the disk apparatus connectors.
The switching apparatus further comprises an array controller switching circuit provided in the switch circuits and upon reception a path switching signal from the array controllers, establishing a connection between an array controller corresponding to the path switching signal and the disk apparatus connectors.
It is preferable that each of the plurality of switch circuits be connected independently from one another to the disk apparatuses.
The switching mechanism may further comprise a control line connector for connecting a control line for transmitting the path switching signal, to the switch circuits.
The switch circuits may provide a first operation state for connecting a first one of the array controllers to the disk apparatuses and a second operation state for connecting a second one of the array controllers to the disk apparatuses.
The switch circuits may provide a first operation state for connecting a first one of the array controllers to the disk apparatuses, a second operation state for connecting a second one of the array controllers to the disk apparatuses, and a third operation state for not connecting any one of the first and second array controllers to the disk apparatuses.
The disk array apparatus according to the present invention comprises: a plurality of switching mechanisms as has been described above, each having an array controller connector; a plurality of disk apparatuses which are connected to the switch mechanisms on one-to-one principle; and a plurality of array controllers connected to the array controller connectors and in response to an instruction from a host computer, writing or reading a data to/from the disk apparatuses.
The array controller which has acquired the control authority outputs the path switching signal to each of the plurality of switching mechanisms.
According to another aspect of the invention, the array controller which has acquired the control authority outputs signals identical to the path switching signal at once to the plurality of switching mechanisms.
REFERENCES:
patent: 5285451 (1994-02-01), Henson et al.
patent: 5867640 (1999-02-01), Aguilar et al.
patent: 4-268621 (1992-09-01), None
patent: 6-48033 (1994-06-01), None
patent: 8-202497 (1996-08-01), None
patent: 8-328758 (1996-12-01), None
patent: 9-258906 (1997-10-01), None
patent: 9-305324 (1997-11-01), None
Japanese Office Action w/partial translation dated Nov. 6, 2001.
McGinn & Gibb PLLC
Namazi Mehdi
Yoo Do Hyun
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