Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-11-20
2003-03-18
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S068000, C327S538000
Reexamination Certificate
active
06535019
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a switching control method for a level shifter, as well as to a self-controlled level shifter, particularly for standard CMOS technology low-power references. The invention relates, particularly but not exclusively, to a CMOS technology application, and in the detailed description which follows reference will be made to this field of application for convenience of illustration only.
BACKGROUND OF THE INVENTION
As is well known, suitable transistors are not available to withstand a high potential across the drain-source junction, as well as at the gate terminal for devices used in low supply voltage processes. As a result, level shifters, e.g. of the cascode type, are usually used for transferring high voltage levels. In particular, VDDL denotes herein a nominal supply voltage level, in particular a low voltage level; VDDH denotes a high voltage level to be transferred; and VREF denotes a reference voltage level, needed to control the different steps of a generic cascode operation.
A conventional shifter of the cascode type is shown generally at
1
in
FIG. 1
, in schematic form.
FIG. 1
illustrates schematically the generators,
2
and
3
, respectively for the reference voltage VREF and the high voltage VDDH, only in terms of their operation. The generators
2
and
3
are driven by the same selection signal SEL.
The shifter
1
basically comprises a differential cell having an input section
4
, comprising a first MOS transistor MN
1
and a second MOS transistor MN
2
and being connected to an input terminal IN of the shifter
1
and to a voltage reference, e.g. a ground reference GND. An output section
5
, is also provided and comprises a third MOS transistor MP
3
and a fourth MOS transistor MP
4
and being connected to the input section
4
, as well as to an output terminal OUT of the shifter
1
and to a reference node X, the latter receiving a reference voltage VREF. In addition, the shifter
1
also includes a biasing section
6
, comprising a fifth MOS transistor MP
5
and a sixth MOS transistor MP
6
and being connected between the output section
5
and a high-voltage reference VDDH.
In particular, the first transistor MN
1
of the input section
4
has a drain terminal connected to the output terminal OUT, a source terminal connected to ground GND, and a gate terminal connected to the input terminal IN through an inverter INV. A second transistor MN
2
of the input section
4
has a drain terminal connected to a drain terminal of the fourth transistor MP
4
of the output section
5
, a source terminal connected to ground GND, and a gate terminal connected to the input terminal IN directly. Furthermore, the third transistor MP
3
of the output section
5
has a source terminal connected to a first internal circuit node A, a drain terminal connected to the output terminal OUT of the shifter
1
, and a gate terminal connected to the reference node X. The fourth transistor MP
4
of the output section
5
has a source terminal connected to a drain terminal of the sixth transistor MP
6
of the biasing section
6
, a drain terminal connected to the drain terminal of the second transistor MN
2
of the input section
4
, and a gate terminal connected to the reference node X. Lastly, the fifth transistor MP
5
of the biasing section
6
has a drain terminal connected to the first internal circuit node A, a source terminal connected to the high-voltage reference VDDH, and a gate terminal cross-connected to the drain terminal of the sixth transistor MP
6
. The latter has a source terminal connected to the high-voltage reference VDDH, and a gate terminal cross-connected to the drain terminal of the fifth transistor MP
5
, i.e. to the first internal circuit node A.
Thus, the third and fifth transistors MP
3
and MP
5
, as well as the fourth and sixth transistors MP
4
and MP
6
, are cascode connected. In particular, transistors MP
3
and MP
5
can be viewed as forming an output leg of the differential cell. The input terminal IN of the shifter
1
receives the selection signal SEL turning on the shifter, and also causing the generators
2
,
3
to generate the voltage references VDDH and VREF. Finally, the second internal circuit node B is connected to an output terminal OUT of the shifter
1
.
It will be now described what happens as the output terminal OUT is switched from a high voltage value VDDH over to a low voltage value VDDL, i.e. upon the high voltage VDDH being de-selected at the output terminal OUT. As shown schematically in
FIGS. 2A
to
2
D, in a steady state, before the high voltage is de-selected at the output terminal OUT, i.e. within the time lapse from ta to tb shown in
FIGS. 2A
to
2
D, the reference voltage VREF is a value such that the third transistor MP
3
enters conduction. This is so while the potential differences between the gate and the drain terminals, |Vgd(MP
3
)|, and between the gate and the source terminals, |Vgs(MP
3
)|, of the third transistor MP
3
are held below the highest admissible value, which is typically much lower than the high voltage value VDDH.
Therefore, the following relation applies generally:
VREF<VA−|Vth
(MP
3
)|
where VA is the voltage at the first internal circuit node A, and Vth(MP
3
) is the threshold voltage of the third transistor MP
3
.
Under these conditions, the gate terminal of the first transistor MN
1
has a low voltage value, and will not interfere with transferring the high voltage VDDH to the output terminal OUT. Thus, the high voltage VDDH will be distributed through the cascoded branch comprising the third and fifth transistors, MP
3
and MP
5
, so that the transistor oxides and junctions are not overly stressed.
The situation is similar, but reversed, in the branch comprising the fourth and the sixth transistors, MP
4
and MP
6
. At a time tb, when the selection signal SEL goes low, the high voltage VDDH at the output terminal OUT decreases, and concurrently therewith, the level of the reference voltage VREF goes high (typically but not necessarily to VDDL). In this way, the stress for the transistors in the structure is attenuated and the level shifter
1
turned off completely.
However, the selection of the first transistor MN
1
, which takes place upon its gate terminal going high, i.e. as the signal SEL on the input terminal IN goes low, will pull the output terminal OUT quickly to ground. This may produce a voltage drop of similar magnitude across the node X due to the capacitive coupling of the gate-drain capacitance Cgd(MP
3
) and source-gate capacitance Cgs(MP
3
) of the third transistor MP
3
(FIG.
1
).
Actually, the value of the voltage variation occurring at the output terminal OUT (from VDDH to 0V) may even pull the node X to negative voltage values, with the reference voltage VREF at node X being a fairly low value, even during the previous high-voltage phase, as shown in FIG.
2
C. This produces stress on the gate oxides and makes correctly biasing the transistors of the shifter
1
more difficult to achieve.
This capacitive effect becomes larger, the larger the load on the output terminal OUT, as when a number of shifters are connected in parallel to the same node. Also, the dimensions W of the transistors MP
1
and MP
3
are proportional to the load to be driven. Thus, the output terminal OUT will have increased inertia, and the coupling between the output terminal OUT and the node X of the reference voltage VREF will be boosted by the dimensional increase of the transistors in shifter
1
, as shown diagrammatically in FIG.
2
D. However, a steadier reference voltage VREF generally involves circulation of a large current through its bias circuit (not shown because it is conventional), resulting in undesired static power consumption and increased power dissipation of the device where the shifter
1
is integrated.
This prior approach, although effective, has an inherent limitation in the operation of de-selection of the high voltage VDDH at the output terminal OUT of the shifter
1
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Cho James H
Jorgenson Lisa K.
STMicroelectronics S.r.l.
Tokar Michael
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