Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-02-13
2004-05-18
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S027000, C326S113000, C327S416000
Reexamination Certificate
active
06737890
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor switching device for switching at high frequencies, especially to a compound semiconductor switching device operating with only one control terminal.
2. Description of the Related Art
Mobile communication devices such as mobile telephones often utilize microwaves in the GHz range, and commonly need switching devices for high frequency signals which are used in switching circuits for changing antennas and switching circuits for transmitting and receiving such signals. A typical example of such a switching device can be found in Japanese Laid-Open Patent Application No. Hei 9-181642. Such a device often uses a field-effect transistor (called FET hereinafter) made on a gallium arsenide (GaAs) substrate, as this material is suitable for use at high frequencies, and developments have been made in forming a monolithic microwave integrated circuit (MMIC) by integrating the aforementioned switching circuits.
FIG. 1A
is a cross-sectional view of a conventional GaAs metal-semiconductor field-effect transistor (MESFET). The GaAs substrate
1
is initially without doping, and has beneath its surface an n-type channel region (or a channel layer)
2
formed by doping with n-type dopants. A gate electrode
3
is placed on the surface of the channel region
2
, forming a Schottky contact, and a source electrode
4
and a drain electrode
5
are placed on both sides of the gate electrode
3
, forming ohmic contacts to the surface of the channel region
2
. In this transistor configuration, a voltage applied to the gate electrode
3
creates a depletion layer within the channel region
2
beneath the gate electrode
3
and thus controls the channel current between the source electrode
4
and the drain electrode
5
.
FIG. 1B
shows the basic circuit configuration of a conventional compound semiconductor switching device called a SPDT (Single Pole Double Throw) switch, using GaAs FETs. The source electrode (or the drain electrode) of each FET (FET
1
and FET
2
) is connected to a common input terminal IN. The drain electrode (or source electrode) of each FET (FET
1
and FET
2
) is connected to respective output terminals (OUT
1
and OUT
2
). The gates of FET
1
and FET
2
are connected to the control terminals Ctl-
1
, Ctl-
2
through resistors R
1
, R
2
, respectively. A pair of complementary signals is applied to the two control terminals, Ctl-
1
, Ctl-
2
. When a high level signal is applied to the control terminal of one of the FETs, the FET changes to an on-state, and a signal fed to the common input terminal IN passes through the FET and reaches one of the output terminals OUT
1
, OUT
2
. The role of the resistors R
1
and R
2
is to prevent the leaking of the high frequency signals through the gate electrodes to the DC voltages applied to the control terminals Ctl-
1
, Ctl-
2
, which are substantially grounded at high frequency.
The conventional compound semiconductor switching device described above is configured so that one of the pair of complementary signal is applied to the gate of FET
1
via the control terminal Ctl-
1
and resistor R
1
and other of the pair of complementary signal is applied to the gate of FET
2
via the control terminal Ctl-
2
and resistor R
2
. Accordingly, two signals, which forms a complementary signal pair, need to be fed to the two control terminals Ctl-
1
, Ctl-
2
. Such a configuration needs two external electrodes for the two control terminals Ctl-
1
, Ctl-
2
when the device is housed in a package, resulting in a large package size. Although it is possible to eliminate one control terminal by introducing an inverter circuit to the switching device, this design requires additional FETs, resulting higher energy consumption and a larger package size.
Furthermore, the conventional GaAs MESFET is a depletion type FET and requires the application of a negative voltage for its operation. Therefore, the conventional compound semiconductor switching device described above requires a negative voltage generating circuit for its operation.
SUMMARY OF THE INVENTION
The semiconductor switching circuit device of this invention operates with only one control terminal without employing inverter circuits. The invention provides a switching circuit device including a common input terminal, a first output terminal and a second output terminal, a first switching element connected to the common input terminal and the first output terminal, a second switching element connected to the common input terminal and the second output terminal, and a control terminal connected to the first switching element and receiving a control signal for the switching device. The device also includes a first connection connecting the control terminal to the second switching element, a second connection connecting the second switching element to a ground, a bias element applying a bias voltage to the first switching element, and a direct current isolation element interrupting direct current between the first switching element and the common input terminal or between the second switching element and the common input terminal.
The invention further provides a semiconductor switching device including a first field effect transistor and a second field effect transistor each comprising a source electrode, a gate electrode and a drain electrode which are formed on a channel layer of the respective transistor. The device also includes a common input terminal connected to the source electrode or the drain electrode of the first and second transistors, a first output terminal connected to the source electrode or the drain electrode of the first transistor which is not connected to the common input terminal, a second output terminal connected to the source electrode or the drain electrode of the second transistor which is not connected to the common input terminal, and a control terminal connected to the gate electrode of the first transistor, which receives a control signal for the switching device. The device further includes a bias element applying a bias voltage to the source electrode or the drain electrode of the first transistor, a first connection connecting the control terminal to the source electrode or the drain electrode of the second transistor, a second connection connecting the gate electrode of the second transistor to a ground, and a direct current isolation element interrupting direct current between the first transistor and the common input terminal or between the second transistor element and the common input terminal.
The switching devices described above may have a predetermined positive voltage applied constantly to the source electrode or the drain electrode of the first transistor. The direct current isolation element may comprise a capacitor and the bias element may comprise a resistor and a power source. The capacitor, the resistor or the both may be integrated into a chip in which the switching elements are formed.
REFERENCES:
patent: 4810911 (1989-03-01), Noguchi
patent: 5350957 (1994-09-01), Cooper et al.
patent: 5497118 (1996-03-01), Ueno et al.
patent: 2002/0117696 (2002-08-01), Hirai et al.
patent: 2002/0118044 (2002-08-01), Hirai et al.
Asano Tetsuro
Hirai Toshikazu
Chang Daniel D.
Morrison & Foerster / LLP
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