Switched pull down emitter coupled logic circuits

Details Switched pull down emitter coupled logic circuits Switched pull down emitter coupled logic circuits

1996-06-07

1998-06-16

Santamauro, Jon

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar transistor

326 18, 326 26, H03K 19086, H03K 19013

Patent

active

057677026

ABSTRACT:
Switched pull down (SPD) ECL circuits have a switching circuit within the pull down portion of the output stage, so that a large portion of the total pull down current is switched to the negative going output node, and so that a small portion of the total pull down current is switched to the positive going output node. The negative going output node has a larger that normal ECL pull down current attached to it. The larger pull down current on the negative going node discharges the output capacitor in a shorter period of time. The shorter discharge time of negative going output results in a shorter fall delay time. Two smaller current sources are connected to each of the two differential ECL outputs to insure that both pull up transistors are forward biased so as to provide an adequate noise margin and insure correct circuit operation. Forward biasing the pull up transistors with a minimum acceptable amount of bias current at the emitters of the output pull up transistors provides proper immunity to noise.

REFERENCES:
patent: 4276485 (1981-06-01), Rydval
patent: 4593211 (1986-06-01), Belforte
patent: 4754171 (1988-06-01), Dasai et al.
patent: 4939393 (1990-07-01), Petty
patent: 4943741 (1990-07-01), Estrada et al.
patent: 5073728 (1991-12-01), Ovens
patent: 5602498 (1997-02-01), Satoh et al.

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