Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2002-01-30
2003-12-16
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S027000, C326S087000
Reexamination Certificate
active
06664805
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to a method for controlling the slew rate of output drivers using switched capacitors.
BACKGROUND OF THE INVENTION
As integrated circuit bus speeds continue to increase, system designers are faced with transmission line issues previously relegated to the analog world. At very high speeds, pc-board traces behave like transmission lines, and reflections occur at all points on the pc-board trace where impedance mismatches exist.
The transition between digital states does not occur instantaneously, but instead occurs over a period of time that is dependent on the physical conditions present on the transmission line. It is well known that signal transitions over a transmission line will suffer a delay known as a propagation delay due to the parasitic resistance, inductance, and capacitance of the line. This delay increases with the length of the line. In addition, it is also well-known that unless the impedance of the transmission line matches that of the load it drives, the signal will degrade due to reflections caused by impedance mismatching.
Signal reflections produce or contribute to a number of problems, including false triggering in clock lines, erroneous bits on data, address, and control lines, clock and signal jitter, and an increase in total emissions from the pc board. One method of reducing these transmission-line effects is to properly terminate the lines. This is especially true when the driver circuit drives multiple loads with differing impedances, the transmission line requires multiple stubs to properly match each of the loads during realtime operation. However, the use of multiple stubs then generates multiple reflections. One way of ensuring proper detection of signal states is to slow the slew rates of the signal's transitioning edges.
However, this competes with the trend towards ever increasing signal frequencies, which results in higher edge rates. Accordingly, a need exists for a technique for controlling the slew rate of signal edge transitions without sacrificing the signal frequency.
SUMMARY OF THE INVENTION
The present invention is a method and circuit for controlling the slew rate of integrated circuit output drivers without sacrificing switching frequency using digitally programmed switched capacitors. In particular, the control input of the output switching device that drives the transmission line to one state or another is charged/discharged to a predetermined first charge level associated with a first step in a sequence of a plurality of charging steps. If a next sequential step in a sequence of a plurality of charging steps exists, the control input of the output switching device is charged/discharged to a predetermined next charge level associated with the next step. The control input of the output switching device is repeated charged/discharged to successively higher/lower charge levels for each step in the sequence of charging steps. When the voltage level on either the control input of the output switching device or the transmission line reaches a predetermined reference voltage, the control input of the output switching device is connected to a maximum ON voltage source
In accordance with a first embodiment of the method of the invention, when a transmission line is to be driven to a particular state by a driver device, within an amount of time much less than the setup time for turning on the driver device, the voltage on the predrive line that controls the driver device is quickly pulled to a level at or very near to the turn-on threshold voltage of the driver device. A sequence of programmed steps sequentially connects an increasing/decreasing capacitance to the predrive line to step up/down the voltage level on the predrive line, resulting in a desired controlled slope of the transmission line signal. Once the voltage level on the transmission line reaches a predetermined reference voltage level (e.g., the saturation voltage), the predrive line is quickly pulled to the “on” voltage level to finish out the transition.
In a second embodiment, the output buffer is configured with a respective pulldown and pullup predriver circuit, which respectively operate to sequentially connect various combinations of a plurality of switched capacitors to the transmission line according to a switched capacitance sequence comprising a plurality of capacitance steps. In the preferred embodiment, the capacitance steps preferably increase/decrease in capacitance for each step in the sequence. Thus, the voltage on transmission line increases/decreases with each step in the switched capacitance sequence. Preferably, a controller allows programmable selection of the combination of switched capacitors to supply a preferred combined parallel capacitance that results in a step-wise linear signal of a desired slope on transmission line.
REFERENCES:
patent: 5283631 (1994-02-01), Koerner et al.
patent: 5717342 (1998-02-01), Lotfi et al.
patent: 5739714 (1998-04-01), Gabara
patent: 6043682 (2000-03-01), Dabral et al.
Agilent Technologie,s Inc.
Tran Anh
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