Switched capacitor DRAM sense amplifier with immunity to...

Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S202000, C365S204000, C365S207000, C365S189090, C365S149000

Reexamination Certificate

active

10931552

ABSTRACT:
A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorbing offset voltages developed as effects of the mismatches. When used in a dynamic random access memory (DRAM) device, this immunity to the mismatches and offsets allows the sense amplifier to reliably detect and refresh small signals.

REFERENCES:
patent: 4985643 (1991-01-01), Proebsting
patent: 5237533 (1993-08-01), Papaliolios
patent: 5339274 (1994-08-01), Shong et al.
patent: 5416371 (1995-05-01), Katayama et al.
patent: 5568440 (1996-10-01), Tsukude et al.
patent: 5708622 (1998-01-01), Ohtani et al.
patent: 5818750 (1998-10-01), Manning
patent: 5828611 (1998-10-01), Kaneko et al.
patent: 5859806 (1999-01-01), Wada
patent: 5940317 (1999-08-01), Manning
patent: 5995163 (1999-11-01), Fossum
patent: 6049496 (2000-04-01), Forbes et al.
patent: 6052307 (2000-04-01), Huber et al.
patent: 6091654 (2000-07-01), Forbes et al.
patent: 6104066 (2000-08-01), Noble et al.
patent: 6115316 (2000-09-01), Mori et al.
patent: 6141239 (2000-10-01), Manning
patent: 6150851 (2000-11-01), Ohmi et al.
patent: 6157688 (2000-12-01), Tamura et al.
patent: 6166367 (2000-12-01), Cho
patent: 6198677 (2001-03-01), Hsu et al.
patent: 6235569 (2001-05-01), Noble et al.
patent: 6246622 (2001-06-01), Sugibayashi
patent: 6262930 (2001-07-01), Mori et al.
patent: 6285613 (2001-09-01), Koya
patent: 6288575 (2001-09-01), Forbes
patent: 6304505 (2001-10-01), Forbes et al.
patent: 6319800 (2001-11-01), Manning
patent: 6341088 (2002-01-01), Sakamoto et al.
patent: 6400629 (2002-06-01), Barth, Jr. et al.
patent: 6437608 (2002-08-01), Miyabe et al.
patent: 6529237 (2003-03-01), Tsay et al.
patent: 6538476 (2003-03-01), Forbes
patent: 6696852 (2004-02-01), Brunolli
patent: 6741104 (2004-05-01), Forbes et al.
patent: 6759657 (2004-07-01), Iida et al.
patent: 6803794 (2004-10-01), Martin et al.
patent: 6809981 (2004-10-01), Baker
patent: 6813190 (2004-11-01), Marotta et al.
patent: 6822904 (2004-11-01), Gallo et al.
patent: 6822919 (2004-11-01), Sahoo
patent: 6842377 (2005-01-01), Takano et al.
patent: 6861634 (2005-03-01), Rossi
patent: 6885396 (2005-04-01), Panicacci et al.
patent: 6885580 (2005-04-01), Baker
patent: 6912167 (2005-06-01), Tam
patent: 6920060 (2005-07-01), Chow et al.
patent: 6937052 (2005-08-01), Tam
patent: 2005/0002218 (2005-01-01), Nazarian
patent: 2005/0018060 (2005-01-01), Takayanagi
patent: 2006/0044012 (2006-03-01), Forbes
patent: 2006/0044907 (2006-03-01), Forbes et al.
U.S. Appl. No. 10/931,786, filed Sep. 1, 2004, Sample and Hold Memory Sense Amplifier.
U.S. Appl. No. 10/931,379, filed Aug. 31, 2004, Capacitively—Coupled Level Restore Circuits for Low Voltage Swing Logic Circuits.
Blalock, Travis N., et al., “A High-speed Sensing Scheme for 1T Dynamic RAMs Utilizing the Clamped Bit-line Sense Amplifier”,IEEE Journal of Solid-State Circuits, 27(4), (Apr. 1992),618-625.
Dhong, Sang H., et al., “High Speed Sensing Scheme for CMIS DRAM's”,IEEE Journal of Solid-State Circuits, vol. 23, No. 1, (Feb. 1998),34-40.
Kuge, Shigehiro , et al., “SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories”,IEEE Journal of Solid-State Circuits, 31(4), (Apr. 1996),pp. 586-591.
Lu, Nicky C., et al., “Half-Vdd Bit-Line Sensing Scheme in CMOS DRAM's”,Journal of Solid-State Circuits, vol. SC-19, No. 4, (Aug. 1984),451-454.
Parke, Stephen A., “Optimization of DRAM Sense Amplifiers for the Gigabit Era”,IEEE, Proceedings of the 40th Midwest Symposium on Circuits and Systems, Sacramento, CA,(1997),pp. 209-212.
Rabaey, Jan M.,Digital Integrated Circuits: A Design Perspective, Section 10.4.2, Prentice Hall Electronics and VLSI Series,(1996),596-603.
Suh, Jung-Won , et al., “Offset-Trimming Bit-Line Sensing Scheme for Gigabit-Scale DRAM's”,IEEE Journal of Solid-State Circuits, 31 (7), (Jul. 1996),pp. 1025-1028.
Suma, Katsuhiro , et al., “An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology”,IEEE Journal of Solid-State Circuits, 29(11), (Nov. 1994),pp. 1323-1329.
U.S. Appl. No. 11/493,961, filed Jul. 27, 2006, Switched Capacitor Dram Sense Amplifier with Immunity to Mismatch and Offsets.
U.S. Appl. No. 11/493,960, filed Jul. 27, 2006, Switched Capacitor Dram Sense Amplifier with Immunity to Mismatch and Offsets.
U.S. Appl. No. 11/485,218, filed Jul. 12, 2006, Sample and Hold Memory Sense Amplifier.
U.S. Appl. No. 11/493,113, filed Jul. 26, 2006, Capacitively—Coupled Level Restore Circuits for Low Voltage Swing Logic Circuits.

No affiliations

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Switched capacitor DRAM sense amplifier with immunity to... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Switched capacitor DRAM sense amplifier with immunity to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Switched capacitor DRAM sense amplifier with immunity to... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3736808

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.