Switched capacitance phase locked loop system

Details Switched capacitance phase locked loop system Switched capacitance phase locked loop system

1994-10-18

1998-07-28

Chin, Wellington

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

331 32, 331365C, H03D 324

Patent

active

057871345

ABSTRACT:
A switched capacitance phase locked loop (PLL) system includes a filter circuit having a scaling channel for scaling the phase error; an integrating channel for integrating the phase error; and a summing device for combining the scaled phase error and the integrated phase error; a voltage controlled oscillator (VCO) responsive to the summing device produces an output; the VCO's gain is proportional to its output clock frequency; the integrating channel includes a switched capacitance integrating circuit for controlling the gain of the integrating channel proportional to the output clock frequency of the VCO and maintaining constant the ratio of, and scaling the product of, the unity gain frequency and the zero frequency of the phase locked loop to keep constant the damping factor and to scale the natural frequency of the phase locked loop with the output clock frequency of the VCO, respectively.

REFERENCES:
patent: 4890299 (1989-12-01), Dolivo et al.
patent: 4894734 (1990-01-01), Fischler et al.
patent: 4929918 (1990-05-01), Chung et al.
patent: 5036294 (1991-07-01), McCarslin
patent: 5258933 (1993-11-01), Johnson et al.
patent: 5384551 (1995-01-01), Kennedy et al.
Philport et al., "A 7mbyte/s (65 MHZ), Mixed-Signal, Magnetic Recording Channel DSP Using Partial, Response Signaling with Maximum Liklihood Detection", IEEE Journal, vol. 29, No. 3 Mar. 1994.

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